View MAX9880AEWM_4973478.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-5139; Rev 0; 7/10
KIT ATION EVALU ILABLE AVA
Low-Power, High-Performance Dual I2S Stereo Audio Codec
General Description Features
1.8V Single-Supply Operation 10.6mW Playback Power Consumption 8kHz to 96kHz Stereo DAC with 96dB Dynamic Range 8kHz to 48kHz Stereo ADC with 82dB Dynamic Range Support for Any Master Clock Between 10MHz to 60MHz Stereo Microphone Inputs Support Digital Microphones Stereo Headphone Amplifiers: Differential (30mW), Single-Ended, or Capacitorless (10mW) Stereo Line Inputs and Stereo Line Outputs Voiceband Filters with Stopband Attenuation Greater than 70dB Battery-Measurement Auxiliary ADC Comprehensive Headset Detection Dual I2S- and TDM-Compatible Digital Audio Interfaces I2C- or SPI-Compatible Control Bus with 3.6V Tolerant Inputs
MAX9880A
The MAX9880A is a high-performance, stereo audio codec designed for portable consumer applications such as smartphones and tablets. Operating from a single 1.8V supply to ensure low-power consumption, the MAX9880A offers a variety of input and output configurations for design flexibility. The MAX9880A can be combined with an audio subsystem, such as the MAX9877 or MAX9879, for a complete audio solution for portable applications. The MAX9880A's stereo differential microphone inputs can support either analog or digital microphones. A stereo single-ended line input, with a configurable preamplifier, can either be recorded by the ADC or routed directly to the headphone or line output amplifiers. The stereo headphone amplifiers can be configured as differential, single ended, or capacitorless. The stereo line outputs have dedicated level adjustment. There are two digital audio interfaces. The primary interface is intended for voiceband applications, while the secondary interface can be used for high performance stereo audio data. Two digital input streams can be processed simultaneously and both digital interfaces support TDM and I2S data formats. The flexible clocking circuitry utilizes any available 10MHz to 60MHz system clock, eliminating the need for an external PLL and multiple crystal oscillators. Both the ADC and DAC can be operated synchronously or asynchronously in master or slave mode. The ADC can be operated from 8kHz to 48kHz sample rates, while the DAC can be operated up to 96kHz. The MAX9880A prevents click and pop during volume changes and during power-up and power-down. Audio quality is further enhanced with user-configurable digital filters for voice and audio data. Voiceband filters provide extra attenuation at the GSM packet frequency and greater than 70dB stopband attenuation at fS/2. An I2C or SPITM serial interface provides control for volume levels, signal mixing, and general operating modes. The MAX9880A is available in space-saving, 48-bump, 2.7mm x 3.5mm, 0.4mm-pitch WLP and 48-pin, 6mm x 6mm TQFN packages.
Ordering Information
PART MAX9880AEWM+ MAX9880AETM+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 48 WLP 48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Simplified Block Diagram
MIC BIAS MASTER CLOCK DIGITAL DIGITAL AUDIO AUDIO INTERFACE INTERFACE 1 2 I2C INTERFACE JACK SENSE/ MEASUREMENT ADC
MIX
DIGITAL FILTERING RIGHT RIGHT DAC
MIX
Applications
Cellular Phones Tablet PCs Portable Gaming Devices Portable Multimedia Players
SPI is a trademark of Motorola, Inc. Functional Diagram/Typical Operating and Pin Configurations appear at end of data sheet.
1
MAX9880A
MIX MIX
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MIX
MIX
LEFT
LEFT DAC
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND.) DVDD, AVDD and PVDD ..........................................-0.3V to +2V DVDDS1, JACKSNS, MICVDD ..............................-0.3V to +3.6V DGND and PGND..................................................-0.1V to +0.1V PREG, REF, REG ....................................-0.3V to (VAVDD + 0.3V) MICBIAS .............................................-0.3V to (VMICVDD + 0.3V) MCLK, LRCLKS1, BCLKS1, SDINS1, SDOUTS1..........................-0.3V to (VDVDDS1 + 0.3V) X1, X2, LRCLKS2, BCLKS2, SDINS2, SDOUTS2, DOUT, MODE ...................-0.3V to (VDVDD + 0.3V) SDA/DIN, SCL/SCLK, CS, IRQ ..............................-0.3V to +3.6V LOUTP, LOUTN, ROUTP, ROUTN, LOUTL, LOUTR ....................(VPGND - 0.3V) to (VPVDD + 0.3V) LINL, LINR, MICLP/DIGMICDATA, MICLN/DIGMICCLK, MICRP/SPDMDATA, MICRN/SPDMCLK ...............................-0.3V to (VAVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Bump WLP (derate 12.5mW/C above +70C) .....1000mW 48-Pin TQFN (derate 37mW/C above +70C) ..........2963mW Junction-to-Ambient Thermal Resistance (JA) (Note 1) 48-Bump WLP ...............................................................80C/W 48-Pin TQFN..................................................................29C/W Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Supply Voltage Range SYMBOL DVDDS1, MICVDD Full-duplex 8kHz mono (Note 3) DAC playback 48kHz stereo (Note 3) Total Supply Current I VDD Full-duplex 48kHz stereo (Note 3) Stereo line-in to line-out only, TA = +25C Shutdown Supply Current Shutdown to Full Operation TA = +25C Analog (AVDD + PVDD + MICVDD) Digital (DVDD + DVDDS1) Analog (AVDD + PVDD + MICVDD) Digital (DVDD + DVDDS1) Analog (AVDD + PVDD + MICVDD) Digital (DVDD + DVDDS1) Analog (AVDD + PVDD + MICVDD) Digital (DVDD + DVDDS1) Analog (AVDD + PVDD + MICVDD) Digital (DVDD + DVDDS1) Excludes PLL lock time CONDITIONS PVDD, DVDD, AVDD MIN 1.65 1.65 TYP 1.8 1.8 5.33 1.4 3.5 2.5 8.4 3.0 4.9 0.012 0.3 2.6 10 MAX 1.95 3.6 8 2 6 4 12 5 8 0.05 2 8 ms A mA UNITS V
2
_______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER DAC (Note 4) Dynamic Range (Note 5) Full-Scale Output Gain Error DR fS = 48kHz, AVVOL = +0dB, TA = +25C Differential mode Capacitorless and single-ended modes DC accuracy, measured with respect to full-scale output 1kHz, 0dB input, highpass filter disabled measured from digital input to analog output; MODE = 0 (IIR voice) f S = 8kHz f S = 16kHz Master or slave mode Slave mode 88 1 0.56 1 1.2 ms 0.59 -75 -15 0 85 85 80 74 0.448 x f S 0.451 x f S 0.1 0.476 x f S 75 0.0161 x fS 0.0312 x fS 0.0321 x fS 0.0625 x fS 0.0042 x fS Hz dB 0 +18 dB dB dB 5 96 dB VRMS % SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9880A
Voice Path Phase Delay
PDLY
Total Harmonic Distortion DAC Attenuation Range DAC Gain Adjust Power-Supply Rejection Ratio
THD AVDAC AV GAIN
fMCLK = 12.288MHz, f S = 48kHz, 0dBFS, measured at headphone outputs VDACA/SDACA = 0xF to 0x0 VDACG = 00 to 11 VAVDD = VPVDD = 1.65V to 1.95V f = 217Hz, VRIPPLE = 100mVP-P, AV VOL = 0dB f = 1kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB
PSRR
f = 10kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB DAC VOICE MODE DIGITAL IIR LOWPASS FILTER (6x Interpolation) Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation f SLP f PLP With respect to f S within ripple; f S = 8kHz to 48kHz -3dB cutoff f < f PLP With respect to f S; f S = 8kHz to 48kHz
Hz dB Hz dB
f > f SLP, f = 20Hz to 20kHz DAC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER DVFLT = 0x1 (Elliptical tuned for 16kHz GSM + 217Hz notch) 5th-Order Passband Cutoff (-3dB from Peak, I2C Register Programmable) DVFLT = 0x2 (500Hz Butterworth tuned for 16kHz) fDHPPB DVFLT = 0x3 (Elliptical tuned for 8kHz GSM + 217Hz notch) DVFLT = 0x4 (500Hz Butterworth tuned for 8kHz) DVFLT = 0x5 (fS/240 Butterworth)
_______________________________________________________________________________________
3
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS DVFLT = 0x1 (Elliptical tuned for 16kHz GSM + 217Hz notch) 5th-Order Stopband Cutoff (-30dB from Peak, I2C Register Programmable) DVFLT = 0x2 (500Hz Butterworth tuned for 16kHz) fDHPSB DVFLT = 0x3 (Elliptical tuned for 8kHz GSM + 217Hz notch) DVFLT = 0x4 (500Hz Butterworth tuned for 8kHz) DVFLT = 0x5 (fS/240 Butterworth) DC Attenuation DCATTEN DVFLT not equal to 000 With respect to f S within ripple; f S = 8kHz to 48kHz Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation f SLP f PLP -3dB cutoff -6.02dB cutoff f < f PLP With respect to f S; f S = 8kHz to 48kHz; f S = 0.5f S to 3.5f S f > f SLP Ripple limit cutoff -3dB cutoff f < f PLP f SLP With respect to f S; f S = 0.5 f S to 3.5 f S f > f SLP 60 0.000625 x fS 90 72 82 84 1 1 1.2 ms f S = 16kHz 0.61 5 60 0.24 x f S 0.33 x f S 0.1 0.5 x f S DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 0, fLRCLK < 50kHz) 0.43 x f S 0.47 x f S 0.50 x f S 0.1 0.58 x f S Hz dB Hz dB MIN TYP 0.0139 x fS 0.0156 x fS 0.0279 x fS 0.0312 x fS 0.0021 x fS 90 dB Hz MAX UNITS
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 1 for fLRCLK > 50kHz) Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Passband Cutoff (-3dB from Peak) DC Attenuation ADC (Note 6) Dynamic Range (Note 5) Full-Scale Input Gain Error (Note 7) DR f S = 8kHz, MODE = 0 (IIR voice), TA = +25C fS = 8kHz to 48kHz, MODE = 1 (FIR audio) (Note 7) Differential MIC input or stereo line inputs, AV PRE = 0dB, AV PGA = 0dB DC accuracy, measured with respect to 80% of fullscale output 1kHz, 0dB input, highpass filter disabled measured from analog input to digital output; MODE = 0 (IIR voice) f S = 8kHz dB VP-P % f PLP Hz dB Hz dB
DAC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER fDHPPB DVFLT = 0x1 (DAI1), DCB = 1 (DAI2) Hz dB
DCATTEN DVFLT = 0x1 (DAI1), DCB = 1 (DAI2)
Voice Path Phase Delay
4
_______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Total Harmonic Distortion ADC Level Adjust SYMBOL THD AVADC CONDITIONS f = 1kHz, f S = 8kHz, TA = +25C, -20dB input AVL/AVR = 0xF to 0x0 VAVDD = 1.65V to 1.95V, input referred f = 217Hz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred Power-Supply Rejection Ratio PSRR f = 1kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred f = 10kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred ADC VOICE MODE DIGITAL IIR LOWPASS FILTER Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation f SLP f PLP With respect to f S within ripple; f S = 8kHz to 48kHz -3dB cutoff f < f PLP With respect to f S; f S = 8kHz to 48kHz f > f SLP, f = 20Hz to 20kHz AVFLT = 0x1 (Elliptical tuned for 16kHz GSM + 217Hz notch) AVFLT = 0x2 (500Hz Butterworth tuned for 16kHz) Passband Cutoff (-3dB from Peak) fAHPPB AVFLT = 0x3 (Elliptical tuned for 8kHz GSM + 217Hz notch) AVFLT = 0x4 (500Hz Butterworth tuned for 8kHz) AVFLT = 0x5 (f S/240 Butterworth) AVFLT = 0x1 (Elliptical tuned for 16kHz GSM + 217Hz notch) AVFLT = 0x2 (500Hz Butterworth tuned for 16kHz) Stopband Cutoff (-30dB from Peak) fAHPSB AVFLT = 0x3 (Elliptical tuned for 8kHz GSM + 217Hz notch) AVFLT = 0x4 (500Hz Butterworth tuned for 8kHz) AVFLT = 0x5 (f S/240 Butterworth) DC Attenuation DCATTEN AVFLT 000 ADC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER With respect to f S within ripple; f S = 8kHz to 48kHz Passband Cutoff f PLP -3dB cutoff -6.02dB cutoff 0.43 x f S 0.48 x f S 0.5 x f S Hz 74 0.0161 x fS 0.0312 x fS 0.0321 x fS 0.0625 x fS 0.0042 x f S 0.0139 x fS 0.0156 x f S 0.0279 x fS 0.0312 x f S 0.0021 x f S 90 dB Hz Hz 0.445 x f S 0.449 x f S 0.1 0.469 x f S Hz dB Hz dB -12 60 80 80 78 72 dB MIN TYP -80 MAX -70 +3 UNITS dB dB
MAX9880A
ADC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER
_______________________________________________________________________________________
5
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Passband Ripple Stopband Cutoff Stopband Attenuation Passband Cutoff (-3dB from Peak) DC Attenuation f SLP SYMBOL f < f PLP With respect to f S; f S = 8kHz to 48kHz CONDITIONS MIN TYP 0.1 0.58 x f S 60 0.000625 x fS 90 8.1 7.6 7.1 6.1 3.1 -5.9 -60 -94 8.6 8.1 7.6 6.6 3.6 -5.4 -55.1 -84 0.5 1 2 4 100 dB dB 9.2 8.6 8.1 7.2 4.3 -4.9 -52 -81 dB MAX UNITS dB Hz dB
f > f SLP, f = 20Hz to 20kHz ADC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER fAHPPB AVFLT = 0x1
Hz dB
DCATTEN AVFLT = 0x1 VOLL/VOLR = 0x00 VOLL/VOLR = 0x01 VOLL/VOLR = 0x02
OUTPUT VOLUME CONTROL
Output Volume Control (Note 8)
VOLL/VOLR = 0x04 VOLL/VOLR = 0x08 VOLL/VOLR = 0x10 VOLL/VOLR = 0x20 VOLL/VOLR = 0x27 VOLL/VOLR = 00x00 to 0x06 (+9dB to +6dB)
Output Volume Control Step Size
VOLL/VOLR = 00x06 to 0x0F (+6dB to +3dB) VOLL/VOLR = 00x0F to 0x17 (-3dB to -19dB) VOLL/VOLR = 00x17 to 0x27 (-19dB to -81dB)
Output Volume Control Mute Attenuation HEADPHONE AMPLIFIER (Note 9) Output Power (Differential Mode) Output Power (Capacitorless Mode) Total Harmonic Distortion + Noise (Differential Mode) Total Harmonic Distortion + Noise (Capacitorless Mode) Total Harmonic Distortion + Noise (Single-Ended Mode) Dynamic Range (Notes 5, 7) POUT POUT
f = 1kHz
f = 1kHz, 0dBFS input, THD < 1%, TA = +25C f = 1kHz, 0dBFS input, THD < 1%, TA = +25C f = 1kHz, -3dBFS input
RL = 16 RL = 32 RL = 16 RL = 32 RL = 16 RL = 32
25
48 30 17 10 -78 -79 -73 -75 -70 -70 -60 -60 -67
mW mW
THD+N
dB
THD+N
f = 1kHz, -3dBFS input
RL = 16 RL = 32
dB
THD+N
f = 1kHz, -3dBFS input
RL = 16 RL = 32
dB
DR
AV VOL = +6dB
77
90
dB
6
_______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Power-Supply Rejection Ratio (Note 7) SYMBOL CONDITIONS VAVDD = VPVDD = 1.65V to 1.95V PSRR f = 217Hz, VRIPPLE = 100mVP-P, AV VOL = 0dB f = 1kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB f = 10kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB AV VOL = -81dB differential mode AV VOL = -81dB, capacitorless mode LOUTP to LOUTN, ROUTP to ROUTN, TA = +25C LOUTP to LOUTN, ROUTP to LOUTN, TA = +25C MIN 60 TYP 80 80 78 72 0.2 mV 0.6 90 45 500 100 -70 dBV Out of shutdown Into shutdown Out of shutdown -70 -70 -70 0.5 LOGL/LOGR = 0x00 Line Output Level Adjust LOGL/LOGR = 0x01 LOGL/LOGR = 0x02 LOGL/LOGR = 0x04 LOGL/LOGR = 0x08 LOGL/LOGR = 0x0F Line Output Mute Attenuation Total Harmonic Distortion + Noise Signal-to-Noise Ratio THD+N f = 1kHz RL = 1k , f = 1kHz, VOUT = 1.4V P-P (Note 9) RL = 1k , LINL/LINR = 20Hz < f < 20kHz 1F to GND A-weighted VAVDD = VPVDD = 1.65V to 1.95V Power-Supply Rejection Ratio PSRR f = 217Hz, VRIPPLE = 100mVP-P, AV VOL = 0dB f = 1kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB f = 10kHz, VRIPPLE = 100mVP-P, AV VOL = 0dB RL = 10k , no sustained oscillations -0.7 -2.6 -4.6 -8.6 -16.6 -31.1 -0.1 -2.1 -4.1 -8.1 -16 -29.9 90 -67 86 90 46 78 80 76 100 pF dB -59 +0.6 -1.6 -3.6 -7.6 -15.6 -29.1 dB dB dB dBV dB pF dB MAX UNITS
MAX9880A
Output Offset Voltage
VOS
Crosstalk Capacitive Drive Capability Click-and-Pop Level (Differential, Capacitorless Modes) Click-and-Pop Level (Single-Ended Mode) LINE OUTPUTS (Note 7) Full-Scale Output
XTALK
Differential, P OUT = 5mW, f = 1kHz Capacitorless mode, P OUT = 5mW, f = 1kHz RL = 32 No sustained oscillations RL = Peak voltage, A-weighted, 32 samples per second Peak voltage, A-weighted, 32 samples per second Into shutdown
VRMS
AVLO
dB
Capacitive Drive Capability
_______________________________________________________________________________________
7
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS PALEN/PAREN = 01 Preamplifier Gain AV PRE PALEN/PAREN = 10 PALEN/PAREN = 11 MIC PGA Gain Common-Mode Rejection Ratio MIC Input Resistance Total Harmonic Distortion + Noise AV PGAM CMRR PGAML/PGAMR = 0x1F PGAML/PGAMR = 0x00 VIN = 100mVP-P, f = 217Hz 30 MIN -0.5 19.5 29.3 -0.5 19.3 TYP 0 20 30 0 19.9 50 50 -80 dB -65 60 80 80 78 72 dB MAX +0.5 20.5 30.5 +0.6 20.4 dB dB k dB UNITS
MICROPHONE AMPLIFIER
RIN_MIC All gain settings AV PRE = 0dB VIN = 1VP-P, f = 1kHz, A-weighted AV PRE = +30dB VIN = 32mV P-P, f = 1kHz, A-weighted VAVDD = 1.65V to 1.95V, input referred f = 217Hz, VRIPPLE = 100mV, AVADC = 0dB, input referred
THD+N
Power-Supply Rejection Ratio
PSRR
f = 1kHz, VRIPPLE = 100mV, AVADC = 0dB, input referred f = 10kHz, VRIPPLE = 100mV, AVADC = 0dB, input referred
MICROPHONE BIAS MICBIAS Output Voltage VMICBIAS ILOAD = 1mA Load Regulation Line Regulation Power-Supply Rejection Ratio Noise Voltage LINE INPUT Full-Scale Input VIN AVLINE = 0dB LIGL/LIGR = 0x00 LIGL/LIGR = 0x01 Line Input Level Adjust AVLINE LIGL/LIGR = 0x02 LIGL/LIGR = 0x04 LIGL/LIGR = 0x08 22.8 20.7 18.9 14.9 6.9 1.0 23.9 21.9 20 16 8 24.9 22.9 20.9 16.9 8.9 dB VP-P PSRR VMICVDD = 1.8V, MBIAS = 0 VMICVDD = 3V, MBIAS = 0 1.48 2.15 1.52 2.2 0.6 1.55 100 90 9.5 1.56 2.25 10 V V/A mV/V dB VRMS
ILOAD = 1mA to 2MA, MBIAS = 0 VAVDD =1.8V, VMICVDD =1.65V to 1.95V, MBIAS = 0 f = 217Hz, VRIPPLE = 100mVP-P f = 10kHz, VRIPPLE = 100mVP-P A-weighted
8
_______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Line Input Mute Attenuation Input Resistance Total Harmonic Distortion + Noise AUXIN INPUT Input DC Voltage Range AUXIN Input Resistance JACK DETECT JACKSNS High Threshold SHDN = 1 VTH1 SHDN = 0 SHDN = 1 VTH2 SHDN = 0 VSENSE RSENSE t GLITCH SHDN = 0 SHDN = 0 1.9 12 8 0.06 x 0.92 x 0.95 x 0.98 x VMICBIAS VMICBIAS VMICBIAS 0.95 x VMICVD 0.17 x VMICBIAS VMICBIAS VMICBIAS 0.08 x VMICVDD VMICVDD 2.3 3.1 300 V k ms 0.10 x
D
MAX9880A
SYMBOL f = 1kHz RIN_LINE THD+N AVLINE = +24dB
CONDITIONS
MIN
TYP 100
MAX
UNITS dB k
20 -74
VIN = 0.1VP-P, f = 1kHz
dB
AUXEN = 1 RIN AUXEN = 1, 0V VAUXIN 0.738
0 10 40
0.738
V M
V
JACKSNS Low Threshold
V
JACKSNS Sense Voltage JACKSNS Sense Resistance JACKSNS Deglitch Period Headphone Sense Threshold 1-BIT SPDM OUTPUT Dynamic Range (Note 5) Output Operational Range Sidetone Gain Adjust Range Voice Path Phase Delay
DR
f S = 48kHz, A-weighted, 0kHz to 20kHz, AV VOL = +0dB; master or slave mode, TA = +25C 0dB signal 1's density 25
90 75
dB %
DIGITAL SIDETONE (MODE = 1 IIR Voice Mode Only) AV STGA Differential output mode MIC input to headphone output, f = 1kHz, HP filter disabled f S = 8kHz f S = 16kHz -60 2.2 ms 1.1 0 dB
PDLY
_______________________________________________________________________________________
9
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER MCLK Input Frequency MCLK Input Duty Cycle Maximum MCLK Input Jitter LRCLK Sample Rate (Note 10) LRCLK Average Frequency Error (Master and Slave Modes) (Note 11) LRCLK PLL Lock Time LRCLK Acceptable Jitter for Maintaining PLL Lock Soft-Start/Stop Time CRYSTAL OSCILLATOR Frequency Maximum Crystal ESR Input Leakage Current Input Capacitance Maximum Load Capacitor DIGITAL INPUT (MCLK) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance DIGITAL INPUTS (SDINS1, BCLKS1, LRCLKS1) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance I IH, I IL TA = +25C -1 10 VIH VIL 200 +1 0.7 x VDVDDS1 0.3 x VDVDDS1 V V mV A pF VIH VIL I IH, I IL TA = +25C -1 10 1.2 0.6 +1 V V A pF I IH, I IL CX1, C X2 CL1, CL2 X1, TA = +25C -1 4 45 Fundamental mode only 12.288 100 +1 A pF pF MHz SYMBOL fMCLK CONDITIONS For any LRCLK sample rate Prescaler = /1 mode /2 or /4 modes Maximum allowable RMS for performance limits DHF = 0 DHF = 1 FREQ1 mode = 0x8 to 0xF PCLK = 192x, 256x, 384x, 512x, 768x, and 1024x FREQ1 mode = Any clock other than above Any allowable LRCLK and PCLK rate, slave mode Rapid lock mode Nonrapid lock mode 8 48 0 0 -0.025 2 12 MIN 10 40 30 100 48 96 0 0 +0.025 7 25 100 10 ms % TYP MAX 60 60 70 UNITS MHz % ps kHz
INPUT CLOCK CHARACTERISTICS
Allowable LRCLK period change from nominal for slave PLL mode at any allowable LRCLK and PCLK rates
ns ms
10
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN 0.7 x VDVDD 0.3 x VDVDD 200 I IH, I IL TA = +25C -1 10 0.65 x VDVDD 0.35 x VDVDD 100 I IH, I IL TA = +25C -35 10 VOL VOH I OL = 3mA I OH = 3mA VDVDDS1 - 0.4 0.4 VDVDD - 0.4 0.4 VDVDD - 0.4 -1 -1 +1 +1 0.4 VDVDD - 0.4 -1 +1 0.2 x VDVDD 0.4 +35 +1 TYP MAX UNITS DIGITAL INPUTS (SDA, SCL, DIN, SCLK, CS, MODE, SDINS2, BCLKS2, LRCLKS2) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL INPUTS (DIGMICDATA) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance CMOS DIGITAL OUTPUTS (BCLKS1, LRCLKS1, SDOUTS1) Output Low Voltage Output High Voltage V V VIH VIL V V mV A pF VIH VIL V V mV A pF
MAX9880A
CMOS DIGITAL OUTPUTS (BCLKS2, LRCLKS2, SDOUTS2) Output Low Voltage Output High Voltage VOL VOH I OL = 3mA I OH = 3mA V V
CMOS DIGITAL OUTPUTS (DOUT) Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage VOL VOH I OL IOH VOL VOH I OL = 1mA, CS = DVDD I OH = 1mA, CS = DVDD MODE = DVDD, DOUT = 0, TA = +25C MODE = DVDD, DOUT = DVDD, TA = +25C I OL = 1mA I OH = 1mA V V A A V V
CMOS DIGITAL OUTPUTS (DIGMICCLK, SPDMDATA, SPDMCLK)
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ) Output High Current Output Low Voltage IOH VOL VOUT = VDVDD, TA = +25C I OL = 3mA A V
______________________________________________________________________________________
11
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MICCLK = 00 DIGMICCLK Frequency DIGMICDATA to DIGMICCLK Setup Time DIGMICDATA to DIGMICCLK Hold Time fMICCLK fMCLK = 12.288MHz MICCLK = 01 MICCLK = 10 t SU,MIC tHD,MIC Either clock edge Either clock edge 20 0 MIN TYP 1.536 2.048 64f S ns ns MHz MAX UNITS
DIGITAL MICROPHONE TIMING CHARACTERISTICS (VDVDD = 1.8V)
SPDM TIMING CHARACTERISTICS SPDMCLK = 00 SPDMCLK Frequency f SPDMCLK fMCLK = 12.288MHz SPDMCLK = 01 SPDMCLK = 10 Rising edge SPDMCLK Minimum, fMCLK = 20MHz to right-channel valid SPDMDATA and falling tDLY,SPDM edge SPDMCLK to leftchannel valid Maximum, fMCLK = 10MHz SPDMDATA tBCLKS tBCLKH tBCLKL tR, tF t SU tHD tDLY CL = 30pF TA = +25C TA = +25C Master operation, CL = 15pF 20 5 0 40 75 30 30 7 1.536 2.048 3.072 15 ns 65 MHz
SPDMCLK to SPDMDATA Delay Time
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 0, VDVDD = 1.8V) BCLK Cycle Time BCLK High Time BCLK Low Time BCLK or LRCLK Rise and Fall Time SDIN or LRCLK to BCLK Setup Time SDIN or LRCLK to BCLK Hold Time SDOUT Delay Time from BCLK Rising Edge TDM Clock Frequency TDM Clock Time High TDM Clock Time Low TDM Short-Sync Setup Time ns ns ns ns ns ns ns
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 1, Figure 3, VDVDD = 1.8V) 1/tCLK tCLKH tCLKL TDM mode (TDM = 1) TDM mode (TDM = 1), TA = +25C TDM mode (TDM = 1), TA = +25C Short TDM mode (TDM = 1, FSW = 0), master mode (MAS = 1) Short TDM mode (TDM = 1, FSW = 0), slave mode (MAS = 0) 20 128 220 220 200 ns 2048 kHz ns ns
t SYNCSET
12
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER TDM Short Sync Hold Time TDM Short Sync Tx Data Delay TDM Long Sync Start Delay TDM Long Sync End Time Setup TDM Data Delay from Clock TDM High-Impedance State Setup from Data TDM Rx Data Setup Time TDM Rx Data Hold Time Serial-Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Fall Time Setup Time for STOP Condition SYMBOL CONDITIONS Short TDM mode (TDM = 1, FSW = 0), master mode (MAS = 1) tSYNCHOLD Short TDM mode (TDM = 1, FSW = 0), slave mode (MAS = 0) Short TDM mode (TDM = 1, FSW = 0) 20 12 3.4 51 40 120 20 20 0 1.3 400 ns ns ns ns ns ns ns kHz s MIN TYP 200 ns MAX UNITS
MAX9880A
t SYNCTX
tCLKSYNC Long TDM mode (TDM = 1, FSW = 1) t ENDSYNC Long TDM mode (TDM = 1, FSW = 1) tCLKTX tHIZOUT t SETUP tHOLD f SCL tBUF TDM mode (TDM = 1) TDM mode (TDM = 1) TDM mode (TDM = 1) TDM mode (TDM = 1)
I2C TIMING CHARACTERISTICS (VDVDD = 1.65V)
tHD,STA tLOW tHIGH t SU,STA tHD,DAT t SU,DAT tR tF tF t SU,STO (Note 12) (Note 12) RPU,SDA = 475 (Note 12) RPU,SDA = 475
0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 300 300 250 900
s s s s ns ns ns ns ns s
______________________________________________________________________________________
13
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Bus Capacitance Pulse Width of Suppressed Spike Minimum SCLK Clock Period Minimum SCLK PulseWidth Low Minimum SCLK PulseWidth High Minimum CS Setup Time Minimum CS Hold Time Minimum CS PulseWidth High Minimum DIN Setup Time Minimum DIN Hold Time Minimum Output Data Propagation Delay Minimum Output Data Enable Time Minimum Output Data Disable Time SYMBOL CB t SP 0 CONDITIONS MIN TYP MAX 400 50 UNITS pF ns
SPI TIMING CHARACTERISTICS tCP tCL tCH tCSS tCSH tCSW tDS tDH tDO tDEN tDZ CL = 50pF 40 18 18 20 20 20 5 5 9 5 5 ns ns ns ns ns ns ns ns ns ns ns
The MAX9880A is 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. Note 3: Clocking all zeros into the DAC. Master mode. Differential headphone mode. Note 4: DAC performance measured at headphone outputs. Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS. f = 20Hz to 20kHz. Note 6: Performance measured using microphone inputs, unless otherwise stated. Note 7: Performance measured using line inputs. Note 8: Performance measured using line inputs to line outputs. Note 9: Performance measured using DAC. fMCLK = 12.288MHz, fLRCLK = 48kHz, unless otherwise stated. Note 10: LRCLK can be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios can exhibit some fullscale performance degradation compared to synchronous integer-related MCLK/LRCLK ratios. Note 11: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate. Note 12: CB is in pF. Note 2:
14
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Typical Operating Characteristics
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc01
MAX9880A
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc02
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
-10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 20Hz 6kHz 1kHz fMCLK = 12.288MHz fLRCLK = 48kHz RLOAD = 32 DIFFERENTIAL MODE
MAX9880A toc03
0 -10 -20 -30 THD+N (dB) fMCLK = 13MHz fLRCLK = 8kHz RLOAD = 32 DIFFERENTIAL MODE
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 3kHz fMCLK = 13MHz fLRCLK = 8kHz RLOAD = 16 BTL MODE 1kHz
0
-40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 POWER OUT (mW) 20Hz 3kHz 1kHz
-80 -90 -100 0 10 20 30 40 50 60 POWER OUT (mW) 20Hz
-90 -100 0 10 20 30 40 50 POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc04
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc05
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
-10 -20 -30 THD+N (dB) -40 -50 -60 -70 6kHz 1kHz fMCLK = 12.288MHz fLRCLK = 96kHz RLOAD = 16 BTL MODE
MAX9880A toc06
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 20Hz 6kHz 1kHz fMCLK = 12.288MHz fLRCLK = 48kHz RLOAD = 16 DIFFERENTIAL MODE
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100 20Hz 6kHz 1kHz fMCLK = 12.288MHz fLRCLK = 96kHz RLOAD = 32 DIFFERENTIAL MODE
0
-80 -90 -100 20Hz 0 10 20 30 40 50 60
60
0
10
20
30
40
50
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc07
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc08
TOTAL HARMONIC DISTORTON + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
-72 -74 -76 THD+N (dB) fMCLK = 12.288MHz fLRCLK = 48kHz RLOAD = 32 DIFFERENTIAL MODE
MAX9880A toc09
-70 fMCLK = 13MHz fLRCLK = 8kHz RLOAD = 32 DIFFERENTIAL MODE
-70 -72 -74 -76 THD+N (dB) fMCLK = 13MHz fLRCLK = 8kHz RLOAD = 16 DIFFERENTIAL MODE 5mW
-70
-75 THD+N (dB)
5mW -80
-78 -80 -82 -84 -86 -88
-78 -80 -82 -84 -86 -88 -90 20mW 5mW
-85
20mW
20mW
-90 10 100 1000 10,000 FREQUENCY (Hz)
-90 10 100 1000 10,000 FREQUENCY (Hz)
10
100
1k FREQUENCY (Hz)
10k
100k
______________________________________________________________________________________
15
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
TOTAL HARMONIC DISTORTON + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc10
TOTAL HARMONIC DISTORTON + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc11
TOTAL HARMONIC DISTORTON + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
-72 -74 -76 THD+N (dB) -78 -80 -82 -84 20mW 5mW fMCLK = 12.288MHz fLRCLK = 96kHz RLOAD = 16 DIFFERENTIAL MODE
MAX9880A toc12
-70 -72 -74 -76 THD+N (dB) -78 -80 -82 -84 -86 -88 -90 10 100 1k FREQUENCY (Hz) 10k 20mW 5mW fMCLK = 12.288MHz fLRCLK = 48kHz RLOAD = 16 DIFFERENTIAL MODE
-70 -72 -74 -76 THD+N (dB) -78 -80 -82 -84 -86 -88 -90 20mW 5mW fMCLK = 12.288MHz fLRCLK = 48kHz RLOAD = 16 DIFFERENTIAL MODE
-70
-86 -88 -90
100k
10
100
1k FREQUENCY (Hz)
10k
100k
10
100
1k FREQUENCY (Hz)
10k
100k
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc13
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc14
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
-10 -20 -30 THD+N (dB) -40 -50 -60 -70 1kHz 6kHz fMCLK = 12.288MHz fLRCLK = 96kHz RLOAD = 32 CAPACITORLESS MODE
MAX9880A toc15
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100 0 5 10 20Hz 3kHz 1kHz fMCLK = 13MHz fLRCLK = 8kHz RLOAD = 32 CAPACITORLESS MODE
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100 20Hz 6kHz 1kHz fMCLK = 12.288MHz fLRCLK = 48kHz RLOAD = 32 CAPACITORLESS MODE
0
-80 -90 -100
20Hz
15
0
5
10
15
0
5
10
15
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc16
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc17
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
fMCLK = 12.288MHz fLRCLK = 96kHz RLOAD = 32 CAPACITORLESS MODE 5mW -75 -80
MAX9880A toc18
-60 -65 -70 fMCLK = 13MHz fLRCLK = 8kHz RLOAD = 32 CAPACITORLESS MODE
-60 -65 -70 THD+N (dB) 1mW -75 -80 fMCLK = 12.288MHz fLRCLK = 48kHz RLOAD = 32 CAPACITORLESS MODE
-60 -65 -70 THD+N (dB)
THD+N (dB)
-75 1mW -80 5mW -85 -90 10 100 1000 10,000 FREQUENCY (Hz)
5mW -85 -90 10 100 1k FREQUENCY (Hz) 10k 100k -85 -90 10 100
20mW
1k FREQUENCY (Hz)
10k
100k
16
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc19
MAX9880A
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
MAX9880A toc20
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE)
-10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100 20Hz 1kHz 6kHz fMCLK = 12.288MHz fLRCLK = 96kHz RLOAD = 32 SINGLE-ENDED MODE
MAX9880A toc21
-40 -45 -50 -55 THD+N (%) -60 -65 -70 -75 -80 -85 -90 0 2 4 6 8 10 20Hz 3kHz 1kHz
-40 -45 -50 -55 THD+N (%) -60 -65 -70 -75 -80 -85 -90 20Hz 6kHz 1kHz
0
12
0
2
4
6
8
10
12
0
3
6
9
12
15
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc22
TOTAL HARMONIC DISTORTON + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX9880A toc23
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE)
fMCLK = 12.288MHz fLRCLK = 96kHz RLOAD = 32 SINGLE-ENDED MODE 5mW
MAX9880A toc24
-60 -65 -70 THD+N (dB) 1mW -75 -80 5mW -85 -90 10 100 1000 fMCLK = 13MHz fLRCLK = 8kHz RLOAD = 32 SINGLE-ENDED MODE
-70 -72 -74 -76 THD+N (dB) -78 -80 -82 -84 -86 -88 -90 5mW 1mW
-60 -65 -70 THD+N (dB) -75 -80 -85 -90
20mW
10,000
10
100
1k FREQUENCY (Hz)
10k
100k
10
100
1k FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (LINE IN TO HEADPHONE)
MAX9880A toc25
TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (LINE IN TO HEADPHONE)
MAX9880A toc26
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (LINE-IN TO HEADPHONE)
LINE-IN PREAMP = +18dB RLOAD = 32I BTL MODE
MAX9880A toc27
0 -10 -20 -30 THD+N (dB) LINE IN PREAMP = +18dB RLOAD = 32 DIFFERENTIAL MODE
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100 20Hz 6kHz 1kHz
10
1 THD+N (%)
-40 -50 -60 -70 -80 -90 0 10 20 30 40 50 POWER OUT (mW) 1kHz 6kHz
0.1
5mW
20Hz
0.01 20mW 0.001 0 10 20 30 40 50 10 100 1000 FREQUENCY (Hz) 10,000 100,000 POWER OUT (mW)
______________________________________________________________________________________
17
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (LINE-IN TO HEADPHONE)
MAX9880A toc28
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO LINE OUT)
MAX9880A toc29
POWER OUT vs. HEADPHONE LOAD
45 40 POWER OUT (mW) 35 30 25 20 15 10 fMCLK = 12.288MHz fLRCLK = 48kHz THD+N = < 0.1% DIFFERENTIAL MODE
MAX9880A toc30 MAX9880A toc36 MAX9880A toc33
10 LINE-IN PREAMP = +0dB RLOAD = 32I BTL MODE
-30 -40 -50 fMCLK = 13MHz fLRCLK = 8kHz 0dBFS
50
1 THD+N (%)
THD+N (dB)
IIR -60 -70
0.1 5mW 0.01
-80 0.001 10 20mW 100 1000 FREQUENCY (Hz) 10,000 100,000 -90 10 100
FIR 1000 10,000
5 0 1 10 100 1000
FREQUENCY (Hz)
HEADPHONE LOAD ()
POWER OUT vs. HEADPHONE LOAD
MAX9880A toc31
POWER OUT vs. HEADPHONE LOAD
fMCLK = 12.288MHz fLRCLK = 48kHz THD+N = < 0.1% SINGLE-ENDED MODE
MAX9880A toc32
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (MICROPHONE TO ADC)
10 fMCLK = 13MHz fLRCLK = 8kHz MICPRE = 0dB VIN = 1VP-P
25 fMCLK = 12.288MHz fLRCLK = 48kHz THD+N = < 0.1% CAPACITORLESS MODE
25
20 POWER OUT (mW)
20 POWER OUT (mW)
1 THD+N (%)
15
15
0.1
10
10
5
5
0.01
0 1 10 100 1000 HEADPHONE LOAD ()
0 1 10 100 1000 HEADPHONE LOAD ()
0.001 10 100 1000 10,000 FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (MICROPHONE TO ADC)
MAX9880A toc34
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (MICROPHONE TO ADC)
MAX9880A toc35
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HEADPHONE)
0 -20 -40 PSRR (dB) -60 -80 VRIPPLE = 100mV
10 fMCLK = 13MHz fLRCLK = 8kHz MICPRE = +20dB VIN = 100VP-P
100 10 THD+N (%) 1 0.1 0.01 fMCLK = 13MHz fLRCLK = 8kHz MICPRE = +30dB VIN = 32mVP-P
1 THD+N (%)
0.1
0.01 -100 -120 10 100 1000 10,000 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz)
0.001 10 100 1000 10,000 FREQUENCY (Hz)
0.001
18
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (MIC TO ADC)
MAX9880A toc37
MAX9880A
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (MICBIAS)
MAX9880A toc38
FFT, DAC TO HEADPHONE, 0dBFS, MCLK = 13MHz, LRCLK = 8kHz
0 -20 AMPLITUDE (dB)
MAX9880A toc39
0 -10 -20 -30 PSRR (dB)
VRIPPLE = 100mV fMCLK = 12.288MHz fLRCLK = 48kHz
0 -20 -40 PSRR (dB) -60 -80 -100 -120
20
-40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k FREQUENCY (Hz)
-40 -60 -80 -100 -120 -140
1
10
100
1k
10k
100k
0
5k
10k FREQUENCY (Hz)
15k
20k
FREQUENCY (Hz)
FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc40
FFT, DAC TO HEADPHONE, 0dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
MAX9880A toc41
FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
NI = 6000 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140
MAX9880A toc42
20 FREQ1 = 0xA 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k
20 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140
20
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
FFT, DAC TO HEADPHONE, 0dBFS, fMCLK = 12.288MHz, fLRCLK = 96kHz
MAX9880A toc43
FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 12.288MHz, fLRCLK = 96kHz
NI = 6000 0 -20 AMPLITUDE (dB) AMPLITUDE (dB) -40 -60 -80 -100 -120 -140
MAX9880A toc44
FFT, DAC TO HEADPHONE, 0dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
0 -20 -40 -60 -80 -100 -120 -140
MAX9880A toc45
20 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k
20
20
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
______________________________________________________________________________________
19
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
MAX9880A toc46
FFT, DAC TO HEADPHONE, 0dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
MAX9880A toc47
FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 13MHz, fLRCLK = 44.1kHz
PLL MODE 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140
MAX9880A toc48
20 PLL MODE 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140 0 5k 10k
FREQUENCY (Hz)
20 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140
20
15k
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
FFT, MICROPHONE TO ADC, 0dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc49
FFT, MICROPHONE TO ADC, -60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc50
FFT, MICROPHONE TO ADC, 0dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140
MAX9880A toc51
0 -20 -40 -60 -80 -100 -120 -140 0 1000 2000 FREQUENCY (Hz) 3000
0 -20 -40 -60 -80 -100 -120 -140
20
AMPLITUDE (dB)
AMPLITUDE (dB)
4000
0
1000
2000 FREQUENCY (Hz)
3000
4000
0
5k
10k FREQUENCY (Hz)
15k
20k
FFT, MICROPHONE TO ADC, -60dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz
MAX9880A toc52
FFT, MICROPHONE TO ADC, 0dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140 AMPLITUDE (dB)
MAX9880A toc53
FFT, MICROPHONE TO ADC, -60dBFS, fMCLK = 13MHz, fLRCLK = 48kHz
-20 -40 -60 -80 -100 -120 -140
MAX9880A toc54
20 NI = 6000 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k
20
0
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
0
5k
10k FREQUENCY (Hz)
15k
20k
20
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
WIDEBAND FFT, DAC TO HEADPHONE, 0dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc55
MAX9880A
WIDEBAND FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz
MAX9880A toc56
DAC IIR HIGHPASS FILTER FREQUENCY RESPONSE, MODE = 0
DVFLT = 0 fLRCLK = 8kHz
MAX9880A toc57
20 FREQ1 = 0xA 0 -20 AMPLITUDE (dB)
0 -20 -40 -60 -80 -100 -120 -140
20 0
DVFLT = 3 AMPLITUDE (dB) -20 -40 -60 DVFLT = 4 -80 -100 0 20k 40k 60k 80k 100k 120k 0 100 200 300 400 500 600 FREQUENCY (Hz) FREQUENCY (Hz)
-40 -60 -80 -100 -120 -140 0 20k 40k 60k 80k 100k 120k FREQUENCY (Hz)
AMPLITUDE (dB)
ADC IIR HIGHPASS FILTER FREQUENCY RESPONSE, MODE = 0
MAX9880A toc58
DAC IIR/FIR LOWPASS FILTER FREQUENCY RESPONSE (8kHz)
MODE = 1 0 AMPLITUDE (dB) -20 MODE = 0 -40 -60 -80 -100
MAX9880A toc59
DAC FIR LOWPASS FILTER FREQUENCY RESPONSE (96kHz)
MAX9880A toc60
20 0
AVFLT = 0
fLRCLK = 8kHz
20
20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100
AVFLT = 3 AMPLITUDE (dB) -20 -40 -60 AVFLT = 4 -80 -100 0 100 200 300 400 500 600 FREQUENCY (Hz)
3000
3200
3400
3600
3800
4000
20k
24k
28k
32k
36k
40k
44k
48k
FREQUENCY (Hz)
FREQUENCY (Hz)
ADC IIR/FIR LOWPASS FILTER FREQUENCY RESPONSE (8kHz)
MAX9880A toc61
SHUTDOWN TO FULL OPERATION (DIFFERENTIAL)
MAX9880A toc62
SHUTDOWN TO FULL OPERATION (SE CLICKLESS)
SCL (1V/div)
MAX9880A toc63
20 MODE = 1 0 AMPLITUDE (dB) -20 MODE = 0 -40 -60 -80 -100 3000 3200 3400 3600 3800
SCL (1V/div)
4000
SPKLP (500mV/div)
SPKL (500mV/div)
TIME (4ms/div)
TIME (40ms/div)
FREQUENCY (Hz)
______________________________________________________________________________________
21
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = , headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.)
SHUTDOWN TO FULL OPERATION (SE FAST TURN ON)
MAX9880A toc64
FULL OPERATION TO SHUTDOWN
MAX9880A toc65
SOFT-START ADC
SCL (1V/div)
MAX9880A toc66
SCL (1V/div)
SCL (1V/div)
TIME (4ms/div)
SPKL-R (500mV/div)
SPKL/R (500mV/div)
SPKLP (500mV/div)
TIME (200s/div)
TIME (1ms/div)
TOTAL HARMONIC DISTORTION + NOISE vs. MCLK FREQUENCY, 0dBFS
MAX9880A toc67
DYNAMIC RANGE vs. MCLK FREQUENCY
VIN = -60dBFS fLRCLK = 48kHz PLL MODE
MAX9880A toc68
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100 10 MCLK FREQUENCY (MHz) fLRCLK = 48kHz PLL MODE
120 110 DYNAMIC RANGE (dB) 100 90 80 70 60
100
10 MCLK FREQUENCY (MHz)
100
LINE INPUT RESISTANCE vs. GAIN SETTING
MAX9880A toc69
AUX CODE vs. INPUT VOLTAGE
MAX9880A toc70
300 250 INPUT RESISTANCE (k) 200 150 100 50 0 -10 -5 0 5 10 15 20
30,000 25,000 AUX CODE (SIGNED DECIMAL) 20,000 15,000 10,000 5000 0 -5000
25
-0.4 -0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
GAIN SETTING (dB)
INPUT VOLTAGE (V)
22
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Pin Configurations
TOP VIEW (BUMP SIDE DOWN)
1 2 X1 3 X2 4 IRQ
MAX9880A
MAX9880A
5 MODE 6 AVDD 7 PREG 8 AGND
+
A
DGND
DVDD B
SDA/DIN
SCL/SCLK
CS
DOUT
REF
MICVDD
MICBIAS
SDINS2 C
LRCLKS2
BCLKS2
N.C.
N.C.
REG
MICLN/ DIGMICCLK
MICRP/ SPDMDATA
MCLK D
SDOUTS2
SDINS1
N.C.
JACKSNS/ AUX
N.C.
MICLP/ DIGMICDATA
MICRN/ SPDMCLK
LRCLKS1 E
BCLKS1
PVDD
LOUTP
ROUTP
PGND
LOUTL
LINL
SDOUTS1 F
DVDDS1
PVDD
LOUTN
ROUTN
PGND
LOUTR
LINR
WLP
ROUTN LOUTN ROUTP LOUTP LOUTR 24 LINR 23 LINL 22 JACKSNS/AUX 21 MICRN/SPDMCLK 20 MICRP/SPDMDATA 19 MICLP/DIGMICDATA 18 MICLN/DIGMICCLK 17 MICBIAS 16 MICVDD 15 AGND *EP 14 N.C. 13 REG 1 SDA/DIN 2 SCL/SCLK 3 X1 4 X2 5 CS 6 DOUT 7 MODE 8 IRQ 9 AVDD 10 11 12 REF N.C. PREG LOUTL PGND PVDD
TOP VIEW
DVDDS1
N.C.
N.C.
36 35 34 33 32 31 30 29 28 27 26 25 SDOUTS1 37 SDINS1 38 LRCLKS1 39 BCLKS1 40 MCLK 41 SDOUTS2 42 SDINS2 43 LRCLKS2 44 BCLKS2 45 DVDD 46 DGND 47 N.C. 48
MAX9880A
+
*EP = EXPOSED PAD
THIN QFN (6mm x 6mm)
______________________________________________________________________________________
N.C.
23
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Pin Description
PIN TQFN-EP 1 2 3 4 5 6 7 WLP B2 B3 A2 A3 B4 B5 A5 NAME SDA/DIN SCL/SCLK X1 X2 CS DOUT MODE FUNCTION I2C Serial-Data Input/Output (MODE = 0). Connect a pullup resistor to DVDD for full output swing. SPI (MODE = 0) compatible serial-data input (MODE = 1). I2C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing. SPI-compatible serial clock input (MODE = 1). Crystal Oscillator Input. Connect load capacitor and one terminal of the crystal to this pin. Acceptable input frequency range: 10MHz to 30MHz. Crystal Oscillator Output. Connect load capacitor and second terminal of the crystal to this pin. SPI-Compatible, Active-Low Chip-Select Input SPI-Compatible Serial-Data Output I2C/SPI Mode Select Input (MODE = 0 for I2C mode, MODE = 1 for SPI mode) Hardware Interrupt Output. IRQ can be programmed to go low when bits in the status register 0x00 are set. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10k pullup resistor to DVDD for full output swing. Analog Power Supply. Bypass to AGND with a 1F capacitor. Converter Reference. Bypass to AGND with a 2.2F capacitor (1.23V nominal). No Connection. Connect to GND. Positive Internal Regulated Supply. Bypass to AGND with a 1F capacitor (1.6V nominal). PREG/2 Voltage Reference. Bypass to AGND with a 1F capacitor (0.8V nominal) Analog Ground Microphone Bias Power Supply. Bypass to AGND with a 1F capacitor. Low-Noise Microphone Bias. Connect a 2.2k output of the microphone. to 470 resistor to the positive
8
A4
IRQ
9 10 11, 14, 28, 33, 35, 48 12 13 15 16 17 18
A6 B6 C4, D4, C5, D6 A7 C6 A8 B7 B8 C7
AVDD REF N.C.
PREG REG AGND MICVDD MICBIAS MICLN/ DIGMICCLK MICLP/ DIGMICDATA MICRP/ SPDMDATA MICRN/ SPDMCLK JACKSNS/AUX
Left Negative Differential Microphone Input. AC-couple a microphone with a series 1F capacitor. Also digital microphone clock output. Selectable through I2C. Left Positive Differential Microphone Input. AC-couple a microphone with a series 1F capacitor. Also digital microphone data input. Selectable through I2C. Right Positive Differential Microphone Input or SPDM Data Output. AC-couple a microphone with a series 1F capacitor. Selectable through I2C. Right Negative Differential Microphone Input. AC-couple a microphone with a series 1F capacitor. Selectable through I2C. Jack Sense. Detects the presence or absence of a jack. See the Headset Detection section. When used as an auxiliary ADC input, AUX is used to measure DC voltages.
19
D7
20 21
C8 D8
22
D5
24
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Pin Description (continued)
PIN TQFN-EP 23 24 25 26 27 29 30 31 32 34 36 37 38 WLP E8 F8 F7 E7 E6, F6 E5 F5 F4 E4 E3, F3 F2 F1 D3 NAME LINL LINR LOUTR LOUTL PGND ROUTP ROUTN LOUTN LOUTP PVDD DVDDS1 SDOUTS1 SDINS1 FUNCTION Left-Line Input. AC-couple analog audio signal to LINL with a 1F capacitor. Right-Line Input. AC-couple analog audio signal to LINR with a 1F capacitor. Right-Line Output Left-Line Output Headphone Power Ground Positive Right-Channel Headphone Output. Connect directly to the load in differential and capacitorless mode. AC-couple to the load in single-ended mode. Negative Right-Channel Headphone Output. Unused in capacitorless and single-ended mode. Negative Left-Channel Headphone Output. Common headphone return in Capacitorless mode. Unused in single-ended mode. Positive Left-Channel Headphone Output Headphone Power Supply. Bypass to PGND with a 1F capacitor. S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1F capacitor. S1 Digital Audio Serial-Data ADC Output S1 Digital Audio Serial-Data DAC Input S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and determines whether the audio data on SDINS1 is routed to the left or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an input when the MAX9880A is in slave mode and an output when in master mode. S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the MAX9880A is in slave mode and an output when in master mode. Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz. S2 Digital Audio Serial-Data ADC Output S2 Digital Audio Serial-Data DAC Input S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and determines whether the audio data on SDINS2 is routed to the left or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the MAX9880A is in slave mode and an output when in master mode. S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the MAX9880A is in slave mode and an output when in master mode. Digital Power Supply. Supply for the digital core and I2C/SPI interface. Bypass to DGND with a 1.0F capacitor. Digital Ground Exposed Pad. Connect the exposed thermal pad to AGND.
MAX9880A
39
E1
LRCLKS1
40 41 42 43
E2 D1 D2 C1
BCLKS1 MCLK SDOUTS2 SDINS2
44
C2
LRCLKS2
45 46 47 --
C3 B1 A1 --
BCLKS2 DVDD DGND EP
______________________________________________________________________________________
25
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Detailed Description
The MAX9880A is a low-power stereo audio codec designed for portable applications requiring minimum power consumption. The stereo playback path accepts digital audio through flexible digital audio interfaces compatible with I2S, TDM, and left-justified audio signals. The MAX9880A can process two simultaneous digital input streams that can be mixed digitally. The primary interface is intended for voiceband applications, while the secondary interface can be used for stereo audio data. An oversampling sigma-delta DAC converts the mixed incoming digital data stream to analog audio and outputs through the stereo headphone amplifier and stereo-line outputs. The headphone amplifier can be configured in differential, single-ended, and capacitorless output modes. The stereo record path has two differential analog microphone inputs with selectable gain. The microphones are powered by an integrated microphone bias. The MAX9880A can retask the left analog microphone input to accept data from up to two digital microphones. An oversampling sigma-delta ADC converts the microphone signals and outputs the digital bit stream over the digital audio interface. An auxiliary ADC allows accurate measurements of DC voltages by retasking the right audio ADC. DC voltages can be read through the registers. The MAX9880A also includes two line inputs. These inputs allow a stereo single-ended signal to be gain adjusted and then recorded by the ADCs and output by the headphone amplifier and line output amplifiers. A jack detection function allows the detection of headphone, microphone, and headset jacks. Insertion and removal events can be programmed to trigger a hardware interrupt and flag a register bit. The MAX9880A's flexible clock circuitry utilizes a programmable clock divider and a digital PLL to allow the DAC and ADC to operate at maximum dynamic range for all combinations of master clock (MCLK) and sample rate (LRCLK) without consuming extra supply current. Any master clock between 10MHz and 60MHz is supported as are all sample rates from 8kHz to 48kHz for the record path and 8kHz to 96kHz for the playback path. Master and slave modes are supported for maximum flexibility. The right analog microphone input can be retasked to output SPDM data. Integrated digital filtering provides a range of notch and highpass filters for both the playback and record paths to limit undesirable low-frequency signals and GSM transmission noise. The digital filtering provides attenuation of out-of-band energy by over 70dB, eliminating audible aliasing. A digital sidetone function allows audio from the record path to be summed into the playback path after digital filtering.
I2C/SPI Registers
Forty internal registers program and report the status of the MAX9880A. Table 1 lists all of the registers, their addresses, and power-on-reset states. Registers 0x00-0x03 are read-only while all of the other registers are read/write. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted. All bits in the read-only registers are not programmable. Read operations of unused bits return zero.
I2C Slave Address The MAX9880A is preprogrammed with a slave address of 0x20 or 0010000. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/write bit to 1 to configure the MAX9880A to read mode. Set the read/write bit to zero to configure the MAX9880A to write mode. The address is the first byte of information sent to the MAX9880A after the START (S) condition.
REGISTER POR ADDRESS STATE (SEE NOTE) 0x00 0x01 0x02 0x03 0* IJDET FREQ1 0 0x04 0x05 -- -- -- -- 0x00 0x00
Table 1. Register Map
REGISTER STATUS Status Jack Status AUX High AUX Low Interrupt Enable SYSTEM CLOCK CONTROL System Clock 0 0 PSCLK R/W ICLD ISLD IULK 0 CLD SLD ULK -- -- -- * -- AUX[15:8] AUX[7:0] 0* * -- JDET -- -- -- R R R R R/W JKSNS[1:0] B7 B6 B5 B4 B3 B2 B1 B0 R/W
26
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 1. Register Map (continued)
REGISTER DAI1 CLOCK CONTROL Stereo Audio Clock Control High Stereo Audio Clock Control Low DAI1 CONFIGURATION Interface Mode A Interface Mode B Time-Division Multiplex DAI2 CLOCK CONTROL Stereo Audio Clock Control High Stereo Audio Clock Control Low DAI2 CONFIGURATION Interface Mode A Interface Mode B Time-Division Multiplex DIGITAL MIXERS DAC-L/R Mixer DIGITAL FILTERING Codec Filters SPDM OUTPUTS Configuration Input REVISION ID Rev ID location (replicated for SPI mode) LEVEL CONTROL Sidetone Stereo DAC Level Voice DAC Level Left ADC Level Right ADC Level Left-Line Input Level Right-Line Input Level Left Volume Control Right Volume Control Left-Line Output Level Right-Line Output Level Left Microphone Gain Right Microphone Gain CONFIGURATION Input Microphone Mode Jack Detect MXINL MICCLK DSLEW JDETEN VSEN 0 MXINR DIGMICL DIGMICR ZDEN JDWK 0 0 AUXCAP AUXGAIN AUXCAL 0 0 0 0 0 0 HPMODE JDEB AUXEN MBIAS 0x22 0x23 0x24 0x25 0x00 0x00 0x00 0x00 R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 DSTS SDACM VDACM 0 0 LILM LIRM VOLLM VOLRM LOLM LORM PALEN PAREN 0 0 0 0 0 0 0 0 VDACG AVLG AVRG 0 0 VOLL VOLR LOGL LOGR PGAML PGAMR 0 DVST SDACA VDACA AVL AVR LIGL LIGR 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REV 0x14 0x42 R/W SPDMCLK SPDML SPDMR 0 0 0 MIXSPDMR 0 0x12 0x13 0x00 0x00 R/W R/W MIXSPDML MODE AVFLT DCB DVFLT 0x11 0x00 R/W MIXDAL MIXDAR 0x10 0x00 R/W MAS2 DL2 WCI2 SEL2 BCI2 SDOEN2 DLY2 SDIEN2 HIZOFF2 DHF TDM2 FSW2 BSEL2 SLOTDLY2[3:0] WS2 0x0D 0x0E 0x0F 0x00 0x00 0x00 R/W R/W R/W PLL2 NI2[7:1] NI2[14:8] RLK2/NI2[0] 0x0B 0x0C 0x00 0x00 R/W R/W MAS1 DL1 WCI1 SEL1 BCI1 SDOEN1 DLY1 HIZOFF1 TDM1 FSW1 BSEL1 SLOTDLY1[3:0] 0 0x08 0x09 0x0A 0x00 0x00 0x00 R/W R/W R/W SDIEN1 DMONO1 PLL1 NI1[7:1] NI1[14:8] RLK1/NI1[0] 0x06 0x07 0x00 0x00 R/W R/W B7 B6 B5 B4 B3 B2 B1 B0 REGISTER POR ADDRESS STATE (SEE NOTE) R/W
MAX9880A
SLOTL1
SLOTR1
SLOTL2
SLOTR2
______________________________________________________________________________________
27
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Table 1. Register Map (continued)
REGISTER POWER MANAGEMENT Enable System Shutdown REVISION ID Revision ID REV 0xFF 0x42 R/W LNLEN SHDN LNREN 0 LOLEN 0 LOREN 0 DALEN XTEN DAREN XTOSC ADLEN 0 ADREN 0 0x26 0x27 0x00 0x00 R/W R/W B7 B6 B5 B4 B3 B2 B1 B0 REGISTER POR ADDRESS STATE (SEE NOTE) R/W
*Reserved.
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
Device Status
Status registers 0x00 and 0x01 are read-only registers that report the status of various device functions. The status register bits are cleared upon reading the status register and are set the next time the event occurs. Registers 0x02 and 0x03 report the DC level applied to AUX. See the ADC section for more details.
Bits in status register 0x00 are set when an alert condition exists. All bits in status register 0x00 are automatically cleared upon a read operation of the register and are set again if the condition remains or occurs following the read of this register.
Table 2. Status Register
REGISTER Status Jack Status AUX High AUX Low B7 CLD B6 SLD B5 ULK -- B4 -- -- AUX[7:0] AUX[15:8] B3 * -- B2 * -- B1 JDET -- B0 -- -- REGISTER ADDRESS (SEE NOTE) 0x00 0x01 0x02 0x03
JKSNS[1:0]
*Reserved.
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
28
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 3. Status Register Bits
BITS CLD FUNCTION Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC. To resolve a clip condition in the signal path, the DAC gain settings and analog input gain settings should be lowered. As the CLD bit does not indicate where the overload has occurred, identify the source by lowering gains individually. Slew Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value. SLD is also set when soft start or stop is complete. Digital PLL Unlock Flag. Indicates that the digital audio PLL has become unlocked and digital signal data is not reliable. Headset Configuration Change Flag. JDET reports changes in JKSNS[1:0]. Changes to JKSNS[1:0] are debounced before setting JDET. The debounce period is programmable using the JDEB bits. JKSNS reports the status of the JACKSNS pin when JDETEN = 1. JKSNS is not debounced and should be interpreted according to the following information. JKSNS[1:0] 00 JKSNS[1:0] 01 10 11 JKMONO DESCRIPTION JACKSNS is below VTH2. JACKSNS is between VTH1 and VTH2. Invalid. JACKSNS is above VTH1. DESCRIPTION
MAX9880A
SLD
ULK JDET
1 Headphone impedance < 8 . Auxiliary Input Measurement. AUX is a 16-bit signed two's complement number representing the voltage measured at JACKSNS/AUX. Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After reading the value, set AUXCAP to 0. AUX Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:
AUX k k = AUX value when AUXGAIN = 1. See AUXGAIN for details on determining the value of k, the calibration constant. Voltage = 0.738V
______________________________________________________________________________________
29
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Hardware Interrupts
Hardware interrupts are reported on the open-drain IRQ pin. When an interrupt occurs, IRQ remains low until the interrupt is serviced by reading the status register 0x00. If a flag is set, it is reported as a hardware interrupt only if the corresponding interrupt enable is set. Each bit enables interrupts for the status flag in the respective bit location in register 0x00.
Table 4. Interrupt Enable
REGISTER Interrupt Enable B7 ICLD B6 ISLD B5 IULK B4 0 B3 0* B2 0* B1 IJDET B0 0 REGISTER ADDRESS (SEE NOTE) 0x04
*Reserved.
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
Clock Control
The MAX9880A can work with a master clock (MCLK) supplied from any system clock within the 10MHz to 60MHz range. Internally the MAX9880A requires a 10MHz to 20MHz clock. A prescaler divides MCLK by 1, 2, or 4 to create the internal clock (PCLK). PCLK is used to clock all portions of the MAX9880A. The MAX9880A can support any sample rate from 8kHz to 48kHz for the digital audio path DAI1 (DAC and ADC) and 8kHz to 96kHz for the DAI2 (high-fidelity DAC path), including all common sample rates (8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz). To accommodate a wide range of system architectures, the MAX9880A supports three main clocking modes: * Normal mode: This mode uses a 15-bit clock divider coefficient to set the sample rate relative to the prescaled MCLK input (PCLK). This allows high
flexibility in both the MCLK and LRCLK frequencies and can be used in either master or slave mode. * Exact integer mode: Common MCLK frequencies (12MHz, 13MHz, 16MHz, and 19.2MHz) can be programmed to operate in exact integer mode for both 8kHz and 16kHz sample rates. In these modes, the MCLK and LRCLK rates are selected by using the FREQ1 bits instead of the NI high, NI low, and PLL control bits. * PLL mode: When operating in slave mode, a PLL can be enabled to lock onto externally generated LRCLK signals that are not integer related to PCLK. Prior to enabling the interface, program NI to the nearest desired ratio and set the NI[0] = 1 to enable the PLL's rapid lock mode. If NI[0] = 0, then NI is ignored and PLL lock time is slower.
Table 5. System and Audio Clock Registers
REGISTER SYSTEM CLOCK CONTROL System Clock DAI1 CLOCK CONTROL Stereo Audio Clock Control High Stereo Audio Clock Control Low DAI2 CLOCK CONTROL Stereo Audio Clock Control High Stereo Audio Clock Control Low PLL2 NI2[7:1] NI2[14:8] RLK2/NI2[0] 0x0B 0x0C PLL1 NI1[7:1] NI1[14:8] RLK1/NI1[0] 0x06 0x07 0 0 PSCLK FREQ1 0x05 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE)
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
30 ______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 5. System and Audio Clock Registers (continued)
BITS FUNCTION MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz. 00 = Disable clock for low-power shutdown. 01 = Select if MCLK is between 10MHz and 20MHz. 10 = Select if MCLK is between 20MHz and 40MHz. 11 = Select if MCLK is greater than 40MHz. Exact Integer Modes. Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or 16kHz sample rates. FREQ1[3:0] 0x00 0x1-0x7 0x8 0x9 FREQ1 0xA 0xB 0xC 0xD 0xE 0xF PCLK (MHz) Reserved 12 12 13 13 16 16 19.2 19.2 LRCLK (kHz) Normal or PLL mode Reserved 8 16 8 16 8 16 8 16 Reserved 1500 750 1625 812.5 2000 1000 2400 1200 PCLK/LRCLK
MAX9880A
PSCLK
Modes 0x8 to 0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK ratio cannot be guaranteed, use PLL mode instead. PLL Mode Enable 0 = (Valid for slave and master mode) The frequency of LRCLK is set by the NI divider bits. In master mode, the MAX9880A generates LRCLK using the specified divide ratio. In slave mode, the MAX9880A expects an LRCLK as specified by the divide ratio. 1 = (Valid for slave mode only) A digital PLL locks on to any externally supplied LRCLK signal. Rapid Lock Mode. To enable rapid lock mode set NI_ to the nearest desired ratio and set RLK_ = 1 before enabling the interface. Normal Mode LRCLK Divider. When PLL = 0, the frequency of LRCLK is determined by NI. See Table 6 for common NI values. For LRCLK = 8kHz to 48kHz operation (DHF = 0 for DAI2): NI = (65,536 x 96 x fLRCLK)/fPCLK fLRCLK = LRCLK frequency f PCLK = Prescaled internal MCLK frequency (PCLK) For LRCLK > 50kHz operation (DHF = 1 for DAI2): NI = (65,536 x 48 x fLRCLK)/fPCLK fLRCLK = LRCLK frequency f PCLK = Prescaled internal MCLK frequency (PCLK)
PLL1/PLL2
RLK1/RLK2
NI1/NI2
______________________________________________________________________________________
31
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Table 6. Common NI Values
LRCLK (kHz) 8 10 11 11.2896 PCLK (MHz): (Note: Any PCLK from 10MHz to 20MHz with any LRCLK 7.8kHz to 50kHz can be used.) 12 12.288 13 14 15 16 16.9344 17 18 18.432 19 20 13A9 11E0 116A 1062 1000 F20 E0B D1B C4A B9C B91 AEC AAB A59 9D5 11.025 1B18 18A2 1800 1694 160D 14D8 135B 1210 10EF 1000 FF0 F0E EB3 E43 D8C 12 1D7E 1ACF 1A1F 1893 1800 16AF 1511 13A9 126F 116A 1159 1062 1000 F86 EBF (DAI1, DAI2 for DHF = 0) 16 2752 23BF 22D4 20C5 2000 1E3F 1C16 1A37 1893 1738 1721 15D8 1555 14B2 13A9 22.05 3631 3144 3000 2D29 2C1A 29AF 26B5 2420 21DE 2000 1FE0 1E1B 1D66 1C85 1B18 24 3AFB 359F 343F 3127 3000 2D5F 2A21 2752 24DD 22D4 22B2 20C5 2000 1F0B 1D7E 32 4EA5 477E 45A9 4189 4000 3C7F 382C 346E 3127 2E71 2E43 2BB1 2AAB 2964 2752 44.1 6C61 6287 6000 5A51 5833 535F 4D6A 4841 43BD 4000 3FC1 3C36 3ACD 390B 3631 48 75F7 6B3E 687D 624E 6000 5ABE 5443 4EA5 49BA 45A9 4564 4189 4000 3E16 3AFB (DAI2 for DHF = 1) 64 4EA5 477E 45A9 4189 4000 3C7F 382C 346E 3127 2E71 2E43 2BB1 2AAB 2964 2752 88.2 6C61 6287 6000 5A51 5833 535F 4D6A 4841 43BD 4000 3FC1 3C36 3ACD 390B 3631 96 75F7 6B3E 687D 624E 6000 5ABE 5443 4EA5 49BA 45A9 4564 4189 4000 3E16 3AFB
Note: Values in bold and underline are exact integers that provide maximum full-scale performance.
Digital Audio Interface
The MAX9880A's dual digital audio interface supports a wide range of operating modes to ensure maximum compatibility. See Figures 1 to 5 for timing diagrams. In master mode, the MAX9880A outputs LRCLK and BCLK, while in slave mode they are inputs. When operating in master mode, BCLK can be configured in a number of ways to ensure compatiblity with other audio devices. The MAX9880A has two sets of digital audio interface pins, S1 and S2, that can be connected to one of two digital audio paths, DAI1 or DAI2. DAI1: Digital Audio Path 1 Operation * DAC path with DR of 90dB and ADC path with DR of 82dB
* DAC path connectable to either S1 or S2 * ADC path connectable to either S1 or S2 * 8kHz to 48kHz sample rates * I2S and TDM-compatible modes * Voice filters or audio filter modes DAI2: Digital Audio Path 2 Operation * * * * High-fidelity DAC path with DR of 96dB DAC path connectable to either S1 or S2 8kHz to 96kHz sample rates I2S and TDM-compatible modes
* Audio FIR filters * No ADC clock control from DAI2 sample clock and no voice filter modes available in DAI2
32
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 7. Digital Audio Interface Registers
REGISTER DAI1 CONFIGURATION Interface Mode A Interface Mode B Time-Division Multiplex DAI2 CONFIGURATION Interface Mode A Interface Mode B Time-Division Multiplex MAS2 DL2 WCI2 SEL2 BCI2 SDOEN2 DLY2 SDIEN2 HIZOFF2 DHF TDM2 FSW2 BSEL2 SLOTDLY2[3:0] WS2 0x0D 0x0E 0x0F MAS1 DL1 WCI1 SEL1 BCI1 SDOEN1 DLY1 SDIEN1 HIZOFF1 DMONO1 TDM1 FSW1 BSEL1 SLOTDLY1[3:0] 0 0x08 0x09 0x0A B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE)
MAX9880A
SLOTL1
SLOTR1
SLOTL2
SLOTR2
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS MAS1/2 FUNCTION Master Mode 0 = The MAX9880A operates in slave mode with LRCLK and BCLK configured as inputs. 1 = The MAX9880A operates in master mode with LRCLK and BCLK configured as outputs. LRCLK Invert (TDM1/2 = 0) 0 = Left-channel data is input and output while LRCLK is low. 1 = Right-channel data is input and output while LRCLK is low. BCLK Invert In master and slave modes: 0 = SDIN is latched into the part on the rising edge of BCLK. SDOUT transitions immediately after the rising edge of BCLK. 1 = SDIN is latched into the part on the falling edge of BCLK. SDOUT transitions immediately after the falling edge of BCLK. In master mode: 0 = LRCLK changes state immediately after the rising edge of BCLK. 1 = LRCLK changes state immediately after the falling edge of BCLK. Delay Mode. DLY1/2 have two different functions in TDM and non-TDM mode. In Non-TDM Mode (TDM1/TDM2 = 0): The functionality is as follows: 1 = The most significant bit of an audio word is latched at the second BCLK edge after the LRCLK transition. 0 = The most significant bit of an audio word is latched at the first BCLK edge after the LRCLK transition. In TDM Mode (TDM1/TDM2 = 1): The functionality is as follows: 1 = The HOLD time on the SDOUT output is increased to be greater than 150ns. 0 = The HOLD time on the SDOUT output is the default (greater than 20ns but less than 150ns). SDOUT High-Impedance Mode 0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9880A, allowing SDOUT to be shared by other devices. 1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9880A. Note: High-impedance mode is intended for use when TDM = 1.
WCI1/2
BCI1/2
DLY1/2
HIZOFF1/2
______________________________________________________________________________________
33
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Table 7. Digital Audio Interface Registers (continued)
BITS TDM1/2 FUNCTION TDM Mode Select 1 = Enables time-division multiplex mode and configures the audio interface to accept PCM data. 0 = Disables time-division multiplex mode. LRCLK signal polarity indicates left and right audio. Frame Sync Width 1 = Frame sync pulse extended to the width of the entire 16-bit first slot 0 data word (TDM1/TDM2 = 1 only; SLOTDLY[0] must be 0 when FSW is set to 1). 0 = Frame sync pulse is 1 bit wide. Word Size 0 = The number of bits per input data word sample is 16 bits, and at least 16 BCLKs per input word are required. 1 = The number of bits per input data word sample is 18 bits, and at least 18 BCLKs per input word transfer is required. These control bits are only recognized when TDM1/TDM2 are cleared to 0. Data Loop. Enabling of these bits provides a bridge from one DAI interface to the other. Data format looping could occur in both directions simultaneously. BIT DL1/2 DL1 = 0 DL1 = 1, SEL2 = 1 DL2 = 0 DL2 = 1, SEL1 = 0 Normal operation Enables SDINS1 to SDOUTS2. Normal operation Enables SDINS2 to SDOUTS1. DESCRIPTION
FSW1/2
WS2
Note: The LRCLKS1 and LRCLKS2 interfaces must be identical. Set the SEL1/2, SDOEN1/2, and SDIEN1/2 bits as shown in the table below to connect the S1 and S2 pins to the DAI1 and DAI2 paths in the MAX9880A. SETTING Connect S1 pins to DAI1 (DAC and ADC) Connect S2 pins to DAI1 (DAC and ADC) SEL1/SEL2 Connect S1 pins (DAC only) to DAI2 Connect S2 pins (DAC only) to DAI2 Connect S1 pins (DAC and ADC) to DAI1, connect S2 to DAI2 (DAC only) Connect S2 pins (DAC and ADC) to DAI1, connect S1 to DAI2 (DAC only) SDOEN1/2 SDOUT Enable 1 = Serial-data output enabled on S1/S2 pins. 0 = Serial-data output disabled on S1/S2 pins. SDIN Enable 1 = Serial-data input to DAI1/2 audio path enabled. 0 = Serial-data input to DAI1/2 audio path disabled. Mono Playback Mode 0 = Stereo data input on DAI1 path is processed separately. 1 = Stereo data input on DAI1 path is mixed to a single channel and routed to both the left and right DAC. When operating in mono voice mode (MODE = 1), stereo data may still be input through DAI1 path and optionally mixed using DMONO = 1. SEL1 0 1 1 X 0 1 SEL2 X 0 0 1 1 0 SDIEN1 1 1 0 0 1 1 SDOEN1 1 0 0 0 1 0 SDIEN2 0 0 1 1 1 1 SDOEN2 0 1 0 0 0 1
SDIEN1/2
DMONO1
34
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 7. Digital Audio Interface Registers (continued)
BITS FUNCTION BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unless sharing the bus with multiple devices. BSEL 000 001 BSEL1/2 010 011 100 101 110 111 DESCRIPTION Off (BCLK output held low) 64x LRCLK (192x internal clock divided by 3) 48x LRCLK (192x internal clock divided by 4) 128x LRCLK (Note: Not a valid BSEL2 choice when DHF = 1.) PCLK/2 PCLK/4 PCLK/8 PCLK/16
MAX9880A
TDM Slot Select. Selects the time slot to use for left/right data according to the following information when operating in time-division multiplex mode. SLOT SLOTL1/2 SLOTR1/2 00 01 10 11 Time slot 1 Time slot 2 Time slot 3 Time slot 4 DESCRIPTION
Slot Data Delay (SLOTDLY1/SLOTDLY2) In TDM Mode: Configures the data delay for each slot in TDM mode of operation according to the following information. In Non-TDM Mode (TDM = 0): SLOTDLY[1:0] does not have any effect. SLOTDLY1/2[3:0] 0xxx SLOTDLY1/2 1xxx x0xx x1xx xx0x xx1x xxx0 xxx1 DHF DESCRIPTION Data for slot 4 begins immediately. Data for slot 4 delayed 1 BCLK cycle. Data for slot 3 begins immediately. Data for slot 3 delayed 1 BCLK cycle. Data for slot 2 begins immediately. Data for slot 2 delayed 1 BCLK cycle. Data for slot 1 begins immediately. Data for slot 1 delayed 1 BCLK cycle (not valid when FSW = 1).
DAC High Sample Rate Mode (DHF) (Valid only for DAI2 audio path) 1 = LRCLK is greater than 50kHz. 4x FIR interpolation filter used. 0 = LRCLK is less than 50kHz. 8x FIR interpolation filter used.
______________________________________________________________________________________
35
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
AUDIO MASTER MODES: LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) SDOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15
7ns (typ) LEFT 1/fS
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
7ns (typ)
7ns (typ) CONFIGURED BY BSEL
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) SDOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7ns (typ) LEFT 1/fS RIGHT
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
7ns (typ)
7ns (typ) CONFIGURED BY BSEL
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7ns (typ) LEFT 1/fS RIGHT
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
7ns (typ)
7ns (typ) CONFIGURED BY BSEL
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2S: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7ns (typ) LEFT 1/fS RIGHT
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
7ns (typ)
7ns (typ) CONFIGURED BY BSEL
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) SDOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15
7ns (typ) LEFT 1/fS
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
7ns (typ)
7ns (typ) CONFIGURED BY BSEL
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED-DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) PERIOD OF MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF fPCLK = 12.288MHz, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode
36 ______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
AUDIO SLAVE MODES: LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0 LRCLK 20ns (min) SDOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15
LEFT 1/fS
RIGHT 0ns (min)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
30ns (min) 75ns (min) 30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
LRCLK 20ns (min) SDOUT
D15
LEFT 1/fS
RIGHT 0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
30ns (min) 75ns (min) 30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
LRCLK 20ns (min) SDIN
D15
LEFT 1/fS
RIGHT 0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
30ns (min) 75ns (min) 30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2S: TDM = 0, WCI = 0, BCI = 0, DLY = 1, SLOTDLY = 0
LRCLK 20ns (min) SDIN
LEFT 1/fS
RIGHT 0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
30ns (min) 75ns (min) 30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1
LRCLK 20ns (min) SDOUT
D15
LEFT 1/fS
RIGHT 0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 5ns (min)
30ns (min) 75ns (min) 30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 2. Digital Audio Interface Audio Slave Mode
______________________________________________________________________________________ 37
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
VOICE (TDM/PCM) MASTER MODES: TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0 7ns (typ) LRCLK 200ns SDOUT 1/fS 7ns (typ)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00 7ns (typ) LRCLK 200ns SDOUT 1/fS 7ns (typ)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0 7ns (typ) LRCLK 200ns SDOUT 1/fS 7ns (typ)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 3. Digital Audio Interface Voice Master Mode
38
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
VOICE (TDM/PCM) SLAVE MODES: TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0 LRCLK 20ns SDOUT 1/fS 0ns (min) 0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 0ns (min)
30ns (min) 75ns (min)
7ns (typ) 30ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0 LRCLK 20ns SDOUT 1/fS 0ns (min) 0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 0ns (min)
30ns (min) 75ns (min)
7ns (typ) 30ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0 LRCLK 20ns SDOUT 1/fS 0ns (min) 0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max) 0ns (min) BCLK 20ns (min) SDIN 0ns (min)
30ns (min) 75ns (min) 30ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 4. Digital Audio Interface Voice Slave Mode
Table 8. Digital Mixers
REGISTER DIGITAL MIXERS DAC-L/R Mixer MIXDAL MIXDAR 0x10 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE)
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS FUNCTION Digital Mixers (MIXDAL/MIXDAR). Selects and mixes the audio source(s) for the DACs according to the information below. MIXDAL/MIXDAR MIXDAL/ MIXDAR 1xxx x1xx xx1x xxx1 SOURCE DAI1 left-channel data DAI1 right-channel data DAI2 left-channel data DAI2 right-channel data
______________________________________________________________________________________
39
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Digital Filtering The MAX9880A incorporates both IIR (voice) and FIR (audio) digital filters to accomodate a wide range of audio sources. The IIR fiilters provide over 70dB of
stopband attenuation as well as selectable highpass filters. The FIR filters provide low power consumption and are linear phase to maintain stereo imaging.
Table 9. Digital Filtering Register
REGISTER DIGITAL FILTERING Codec Filters MODE AVFLT DCB DVFLT 0x11 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE)
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS MODE FUNCTION Digital Audio Filter Mode. Selects the filtering mode for the DAI1 DAC and ADC signal paths. 0 = IIR voice filters 1 = FIR audio filters ADC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path. MODE = 0 Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical Operating Characteristics section for details on each filter. MODE = 1 0x0 = DC-blocking filter disabled. 0x1 = DC-blocking filter enabled. 1 = DC-blocking filter for DAI2 enabled. 0 = DC-blocking filter for DAI2 disabled. DAC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path. MODE = 0 Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical Operating Characteristics section for details on each filter. MODE = 1 0x0 = DC-blocking filter disabled. 0x1 = DC-blocking filter enabled.
AVFLT
DCB
DVFLT
Table 10. IIR Highpass Digital Filters
CODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 to 0x7 Elliptical Butterworth Elliptical Butterworth Butterworth 16 16 8 8 8 to 24 Reserved FILTER TYPE VALID SAMPLE RATE (kHz) HIGHPASS CORNER FREQUENCY Disabled 256Hz 500Hz 256Hz 500Hz f S/240 Yes No Yes No No 217Hz NOTCH
40
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 11. SPDM Output Registers
REGISTER Configuration Input B7 B6 B5 SPDML MIXSPDML B4 SPDMR B3 0 B2 0 B1 0 B0 0 REGISTER ADDRESS (SEE NOTE) 0x12 0x13
MAX9880A
SPDMCLK
MIXSPDMR
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
The MAX9880A supports stereo PDM outputs. The PDM signals consist of PDM data outputs (SPDMDATA) and a clock output (SPDMCLK). The mixer at the input to the
PDM modulators allows a mix/mux of the audio digital data stream from the digital audio ports SDINS1 and SDINS2. Figure 5 shows the SPDM interface timing diagram.
SPDMCLK tDLY, DSD tDLY, DSD
SPDMDATA
LEFT CH
RIGHT CH
LEFT CH
RIGHT CH
Figure 5. SPDM Timing Diagram
BITS SPDM Clock Rate (SPDMCLK) 00 = SPDMCLK is set to PCLK/8. 01 = SPDMCLK is set to PCLK6. 10 = SPDMCLK is set to PCLK/4. 11 = Reserved 0 = Disables SPDM data. 1 = Enables SPDM data.
FUNCTION
SPDMCLK
SPDML/SPDMR
SPDM Input Mixers. Selects and mixes the audio source(s) for the SPDM output according to following information. MIXSPDML/MIXSPDMR MIXDSPDM/ MIXSPDMR 1xxx x1xx xx1x xxx1 SOURCE DAI1 left-channel data DAI1 right-channel data DAI2 left-channel data DAI2 right-channel data
______________________________________________________________________________________
41
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Digital Gain Control The MAX9880A includes gain adjustment for the playback and record paths. Independent gain adjustment is
provided for the two record channels. Sidetone gain adjustment is also provided to set the sidetone level relative to the playback level.
Table 12. Digital Gain Registers
REGISTER LEVEL CONTROL Sidetone Stereo DAC Level Voice DAC Level Left ADC Level Right ADC Level 0 0 0 0 DSTS SDACM VDACM 0 0 0 0 VDACG AVLG AVRG 0 DVST SDACA VDACA AVL AVR 0x15 0x16 0x17 0x18 0x19 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE)
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS Digital Sidetone Source Mixer 00 = No sidetone selected. 01 = Left ADC 10 = Right ADC 11 = Left and right ADC Digital Sidetone Level Control. All gain settings are relative to the ADC input voltage. Differential Headphone Output Mode SETTING GAIN (dB) SETTING GAIN (dB) SETTING 0x00 Off 0x0B -20 0x16 0x01 0 0x0C -22 0x17 0x02 -2 0x0D -24 0x18 0x03 -4 0x0E -26 0x19 0x04 -6 0x0F -28 0x1A 0x05 -8 0x10 -30 0x1B 0x06 -10 0x11 -32 0x1C 0x07 -12 0x12 -34 0x1D 0x08 -14 0x13 -36 0x1E 0x09 -16 0x14 -38 0x1F 0x0A -18 0x15 -40 -- Capacitorless and Single-Ended Headphone Output Mode SETTING GAIN (dB) SETTING GAIN (dB) SETTING 0x00 Off 0x0B -25 0x16 0x01 -5 0x0C -27 0x17 0x02 -7 0x0D -29 0x18 0x03 -9 0x0E -31 0x19 0x04 -11 0x0F -33 0x1A 0x05 -13 0x10 -35 0x1B 0x06 -15 0x11 -37 0x1C 0x07 -17 0x12 -39 0x1D 0x08 -19 0x13 -41 0x1E 0x09 -21 0x14 -43 0x1F 0x0A -23 0x15 -45 -- FUNCTION
DSTS
DVST
GAIN (dB) -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -- GAIN (dB) -47 -49 -51 -53 -55 -57 -59 -61 -63 -65 --
42
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 12. Digital Gain Registers (continued)
BITS SDACM/ VDACM DAC Mute Enable 0 = No mute 1 = Mute DAC Gain 00 = 0dB 01 = +6dB 10 = +12dB 11 = +18dB Note: VDACG is only used when MODE = 0. If MODE = 1, then the DAC gain is always 0dB. DAC Level Control. VDACA/SDACA works in all modes. SETTING 0x0 0x1 VDACA/SDACA 0x2 0x3 0x4 0x5 0x6 0x7 GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 SETTING 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF GAIN (dB) -8 -9 -10 -11 -12 -13 -14 -15 FUNCTION
MAX9880A
VDACG
ADC Gain Control. Applies the specified gain to the digital ADC paths according to the following information. SETTING AVLG/AVRG 0x0 0x1 0x2 0x3 ADC Left/Right Level Control SETTING 0x0 0x1 AVL/AVR 0x2 0x3 0x4 0x5 0x6 0x7 GAIN (dB) +3 +2 +1 0 -1 -2 -3 -4 SETTING 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF GAIN (dB) -5 -6 -7 -8 -9 -10 -11 -12 GAIN (dB) 0 +6 +12 +18
______________________________________________________________________________________
43
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Line Inputs
The MAX9880A include one pair of single-ended line inputs. When enabled the line inputs connect directly to the headphone amplifier and line outputs and can be optionally connected to the ADC for recording.
Playback Volume
The MAX9880A incorporates volume and mute control to allow level control for the playback audio path. Program registers 0x1C and 0x1D to set the desired volume.
Line Output Level
The MAX9880A incorporates gain and mute control to allow level control for the line outputs.
Table 13. Line Input Registers
REGISTER Left-Line Input Level Right-Line Input Level B7 0 0 B6 LILM LIRM B5 0 0 B4 0 0 B3 B2 LIGL LIGR B1 B0 REGISTER ADDRESS (SEE NOTE) 0x1A 0x1B
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS LILM/LIRM FUNCTION Line Input Left/Right Playback Mute 0 = Line input is connected to the headphone amplifiers. 1 = Line input is disconnected from the headphone amplifiers. Line Input Left/Right Gain SETTING 0x0 0x1 LIGL/LIGR 0x2 0x3 0x4 0x5 0x6 0x7 GAIN (dB) +24 +22 +20 +18 +16 +14 +12 +10 SETTING 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF GAIN (dB) +8 +6 +4 +2 0 -2 -4 -6
Table 14. Playback Volume Registers
REGISTER Left Volume Control Right Volume Control B7 0 0 B6 VOLLM VOLRM B5 B4 B3 VOLL VOLR B2 B1 B0 REGISTER ADDRESS (SEE NOTE) 0x1C 0x1D
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS FUNCTION Left/Right Playback Mute. VOLLM and VOLRM mute both the DAC and line input audio signals. 0 = Audio playback is unmuted. 1 = Audio playback is muted. Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
VOLLM/ VOLRM
44
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 14. Playback Volume Registers (continued)
BITS FUNCTION Left/Right Playback Volume. VOLL and VOLR control the playback volume for both the DAC and line input audio signals. SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB) 0x00 +9 0x0E -2 0x1C -39 0x01 +8.5 0x0F -3 0x1D -43 0x02 +8 0x10 -5 0x1E -47 0x03 +7.5 0x11 -7 0x1F -51 0x04 +7 0x12 -9 0x20 -55 0x05 +6.5 0x13 -11 0x21 -59 0x06 +6 0x14 -13 0x22 -63 0x07 +5 0x15 -15 0x23 -67 0x08 +4 0x16 -17 0x24 -71 0x09 +3 0x17 -19 0x25 -75 0x0A +2 0x18 -23 0x26 -79 0x0B +1 0x19 -27 0x27 -81 0x0C 0 0x1A -31 0x28 to 0x3F MUTE 0x0D -1 0x1B -35 Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the singleended and capacitorless modes, the actual gain is 5dB lower. Assuming LOGL/LOGR = 0dB, line output gain is 6dB lower.
MAX9880A
VOLL/VOLR
Table 15. Output Line-Level Registers
REGISTER Left-Line Output Level Right-Line Output Level B7 0 0 B6 LOLM LORM B5 0 0 B4 0 0 B3 B2 LOGL LOGR B1 B0 REGISTER ADDRESS (SEE NOTE) 0x1E 0x1F
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS FUNCTION Left/Right Line Output Mute. LOLM and LORM mute both the DAC and line input audio signals. 0 = Line output is unmuted. 1 = Line output is muted. Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set the output is muted immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0). Left/Right Line Output Gain. LOGL and LOGR set the line output gain according to the following information. SETTING 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 GAIN (dB) 0 -2 -4 -6 -8 -10 -12 -14 SETTING 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F GAIN (dB) -16 -18 -20 -22 -24 -26 -28 -30
LOLM/LORM
LOGL/LOGR
______________________________________________________________________________________
45
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Microphone Inputs
Two differential microphone inputs and a low noise 1.5V microphone bias for powering the microphones are provided by the MAX9880A. In typical applications, the left microphone records a voice signal and the right microphone records a background noise signal. In applications that require only one microphone, use the left microphone input and disable the right ADC. The microphone signals are amplified by two stages of gain and then routed to the ADCs. The first stage offers selectable 0dB, 20dB, or 30dB settings. The second stage is a programmable gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps. Zero-crossing detection is included on the PGA to minimize zipper noise while making gain changes. See Figure 6 for a detailed diagram of the microphone input structure.
MAX9880A
MICBIAS 1.5V 0/20/30dB VREG MICLP MICLN PREAMP PGA 0dB TO +20dB ADC L
-
0/20/30dB VREG MICRP MICRN PREAMP PGA 0dB TO +20dB ADC R
Figure 6. Microphone Input Block Diagram
Table 16. Microphone Input Register
REGISTER Left Microphone Gain Right Microphone Gain B7 0 0 B6 PALEN PAREN B5 B4 B3 B2 PGAML PGAMR B1 B0 REGISTER ADDRESS (SEE NOTE) 0x20 0x21
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS FUNCTION Left/Right Microphone Preamplifier Gain. Enables the microphone circuitry and sets the preamplifier gain. 00 = Disabled 01 = 0dB 10 = +20dB 11 = +30dB
PALEN/ PAREN
46
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 16. Microphone Input Register (continued)
BITS SETTING 0x00 0x01 0x02 0x03 PGAML/ PGAMR 0x04 0x05 0x06 0x07 0x08 0x09 0x0A GAIN (dB) +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 FUNCTION Left/Right Microphone Programmable Gain Amplifier SETTING 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 to 0x1F GAIN (dB) +9 +8 +7 +6 +5 +4 +3 +2 +1 0
MAX9880A
ADC
The MAX9880A includes 2-bit ADCs. The first ADC is used to record left-channel microphone and line-input audio signals. The second ADC can be used to record right-channel microphone and line-input signals or it can be configured to accurately measure DC voltages. When measuring DC voltages both the left and right ADC must be enabled by setting ADLEN and ADREN in register 0x26. The input to the second ADC is JACKSNS/ AUX and the output is reported in AUX (registers 0x02 and 0x03). Since the audio ADC is used to perform the measurement, the digital audio interface must be properly configured. If the left ADC is being used to convert audio, then the DC measurement is performed at the same sample rate. When not using the left ADC, configure the digital interface for a 48kHz sample rate to ensure the fastest possible settling time. To ensure accurate results, the MAX9880A includes two calibration routines. Calibrate the ADC each time the MAX9880A is powered on. Calibration settings are not lost if the MAX9880A is placed in shutdown. When making a measurement, set AUXCAP to 1 to prevent AUX from changing while reading the registers.
Setup Procedure 1) Ensure a valid MCLK signal is provided and configure PSCLK appropriately.
2) Choose a clocking mode. The following options are possible: a. Slave mode with LRCLK and BCLK signals provided. The measurement sample rate is determined by the external clocks. b. Slave mode with no LRCLK and BCLK signals provided. Configure the device for normal clock mode using the NI ratio. Select fS = 48kHz to allow for the fastest settling times. c. Master mode with audio. Configure the device in normal mode using the NI ratio or exact integer mode using FREQ1 as required by the audio signal. d. Master mode without audio. Configure the device in normal mode using the NI ratio. Select fS = 48kHz to allow for the fastest settling times. 3) Ensure jack sense is disabled. 4) Enable the left and right ADC; take the MAX9880A out of shutdown.
______________________________________________________________________________________
47
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Offset Calibration Procedure Perform before the first DC measurement is taken after applying power to the MAX9880A.
1) Enable the AUX input (AUXEN = 1). 2) Enable the offset calibration (AUXCAL = 1). 3) Wait the appropriate time (see Table 17). 4) Complete calibration (AUXCAL = 0).
Complete DC Measurement Example fMCLK = 13MHz, slave mode, BCLK, and LRCLK are not externally supplied. 1) Configure the digital audio interface for fs = 48kHz (PSCLK = 01, FREQ1 = 0x0, PLL = 0, NI = 0x5ABE, MAS = 0).
2) Disable jack sense (JDETEN = 0). 3) Enable the left and right ADC; take the MAX9880A out of shutdown (ADLEN = ADREN = SHDN = 1). 4) Calibrate the offset: a. Enable the AUX input (AUXEN = 1). b. Enable the offset calibration (AUXCAL = 1). c. Wait 40ms. d. Complete calibration (AUXCAL = 0). 5) Calibrate the gain: a. Start gain calibration (AUXGAIN = 1). b. Wait 40ms. c. Freeze the measurement results (AUXCAP = 1). d. Read AUX and store the value in memory to correct all future measurements (k = (AUX[15:0]). e. Complete calibration (AUXGAIN = AUXCAP = AUXEN = 0). 6) Measure the voltage on JACKSNS/AUX. a. Enable the AUX input (AUXEN = 1). b. Wait 40ms. c. Freeze the measurement results (AUXCAP = 1). d. Read AUX and correct with the gain calibration value. e. Complete measurement (AUXCAP = 0). 7) DC measurement is complete.
Gain Calibration Procedure Perform the first time a DC measurement is taken after applying power to the MAX9880A or if the temperature changes significantly. 1) Enable the AUX input (AUXEN = 1). 2) Start gain calibration (AUXGAIN = 1). 3) Wait the appropriate time (see Table 17). 4) Freeze the measurement results (AUXCAP = 1). 5) Read AUX and store the value in memory to correct all future measurements (k = (AUX[15:0], k is typically 19,500). 6) Complete calibration (AUXGAIN = AUXCAP = 0). DC Measurement Procedure Perform after offset and gain calibration are complete. 1) Enable the AUX input (AUXEN = 1).
2) Wait the appropriate time (see Table 17). 3) Freeze the measurement results (AUXCAP = 1). 4) Read AUX and correct with the gain calibration value AUX[15 : 0] . V AUX = 0. 738 k 5) Complete measurement (AUXCAP = 0).
Table 17. AUX ADC Wait Times
LRCLK (kHz) 48 44.1 32 24 22.05 16 12 11.025 8 WAIT TIME (ms) 40 44 60 80 90 120 160 175 240
48
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 18. ADC Input Register
REGISTER Input B7 MXINL B6 B5 MXINR B4 B3 AUXCAP B2 AUXGAIN B1 AUXCAL B0 AUXEN REGISTER ADDRESS (SEE NOTE) 0x22
MAX9880A
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS FUNCTION Left/Right ADC Audio Input Mixer 00 = No input selected 01 = Left/right analog microphone 10 = Left/right line input 11 = Left/right analog microphone + line input Note: If the right line input is disabled, then the left line input is connected to both mixers. Enabling the left and right digital microphones disables the left and right audio mixer, respectively. See the DIGMICL/ DIGMICR bit description for more details. Auxiliary Input Capture 0 = Update AUX with the voltage at JACKSNS/AUX. 1 = Hold AUX for reading. Auxiliary Input Gain Calibration 0 = Normal operation 1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference. While in this mode, read the AUX register and store the value. Use the stored value as a gain calibration factor, k, on subsequent readings. Auxiliary Input Offset Calibration 0 = Normal operation 1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal offsets. AUXCAL must remain set for time indicated in Table 17 to guarantee an accurate offset calibration. Auxiliary Input Enable 0 = Use JACKSNS/AUX for jack detection. 1 = Use JACKSNS/AUX for DC measurements. Note: Set MXINR = 00, ADLEN = 1, and ADREN = 1 when AUXEN = 1.
MXINL/MXINR
AUXCAP
AUXGAIN
AUXCAL
AUXEN
______________________________________________________________________________________
49
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Digital Microphone Input
The MAX9880A can accept audio from up to two digital microphones. When using digital microphones, the left analog microphone input is retasked as a digital microphone input. The right analog microphone input is still available to allow a combination of analog and digital microphones to be used. Figure 7 shows the digital microphone interface timing diagram.
1/fMICCLK
DIGMICCLK
tHD, MIC
tSU, MIC
tHD, MIC
tSU, MIC
DIGMICDATA
LEFT
RIGHT
LEFT
RIGHT
Figure 7. Digital Microphone Timing Diagram
Table 19. Digital Microphone Input Register
REGISTER Microphone Grayed boxes = Not used. B7 B6 B5 DIGMICL B4 DIGMICR B3 0 B2 0 B1 0 B0 MBIAS REGISTER ADDRESS (SEE NOTE) 0x23
MICCLK
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS Digital Microphone Clock 00 = PCLK/8 01 = PCLK/6 10 = 64f S (high jitter clock) 11 = Reserved Digital Left/Right Microphone Enable DIGMICL 0 DIGMICL/ DIGMICR 0 1 1 DIGMICR 0 1 0 1 LEFT ADC INPUT ADC input mixer Line input (left analog microphone unavailable) Left digital microphone Left digital microphone RIGHT ADC INPUT ADC input mixer Right digital microphone ADC input mixer Right digital microphone FUNCTION
MICCLK
Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1. MBIAS Microphone Bias Output Voltage Set MBIAS = 0 for nominal output of 1.52V (VMICVDD = 1.8V) Set MBIAS = 1 for nominal output of 2.2V (VMICVDD = 3V)
50
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Mode Configuration
The MAX9880A includes circuitry to minimize click-andpop during volume changes, detect headsets, and configure the headphone amplifier mode. Both volume slewing and zero-crossing detection are included to ensure click-and-pop free volume transitions. Headset Detection Overview The MAX9880A contains headset detect circuitry that is capable of detecting the insertion or removal of a plug and providing information to assist the system controller in determining the configuration of an inserted plug. If programmed to do so, upon insertion or removal of a plug, the IRQ output is asserted (pulled low). Table 20 shows the registers associated with the jack detect function in MAX9880A.
MAX9880A
Table 20. Jack-Detect Registers
REGISTER Status Jack Status Interrupt Enable Jack Detect B7 CLD ICLD JDETEN B6 SLD ISLD 0 B5 ULK -- IULK JDWK B4 -- -- 0 0 B3 -- -- 0 0 B2 -- -- 0 0 B1 JDET -- IJDET JDEB B0 -- -- 0 REGISTER ADDRESS 0x00 0x01 0x04 0x25 POR STATE -- -- 0x00 0x00 R/W R R R/W R/W
JKSNS[1:0]
Grayed boxes = Not used.
Jack Configuration Change Flag (JDET) 1 = Jack configuration has changed. 0 = No change in jack configuration. JDET reports changes in JKSNS[1:0]. Changes to JKSNS[1:0] are debounced before setting JDET. The debounce period is programmable using the JDEB bits. Jack status register 0x01 is a read-only register that reports the status of the jack-detect circuitry when enabled. Jack Sense (JKSNS) JKSNS[1:0] reports the status of the JACKSNS pin when JDETEN = 1. JKSNS[1:0] should be interpreted according to Table 21. Jack-Detect Interrupt Enable (IJDET) Hardware interrupts are reported on the open-drain IRQ pin. When an interrupt occurs, IRQ remains low until the interrupt is serviced by reading the status register 0x00. If a flag is set, it is reported as a hardware interrupt only if the corresponding interrupt enable is set. Each bit enables interrupts for the status flag in the respective bit location in register 0x00. So IJDET must be set to enable interrupts for jack detect.
Jack-Detect Enable (JDETEN) Enables the jack-detect circuitry. Jack-Sense Weak Pullup (JDWK) Enables a weak internal pullup current for reduced power loss when the chip is in shutdown or the MICBIAS is disabled. JDWK = 0 enables a 2.2k pullup to obtain full jackdetect operation. This mode can be used to detect insertion and removal of a plug as well as distinguish between headphone and headset accessories. JDWK = 1 enables a 4A pullup current source when SHDN = 0 or MICBIAS disabled. In this power-saving configuration, the circuit can detect insertion and removal of a plug but cannot distinguish between headphone and headset accessories. The recommended usage follows: Set JDWK = 0 (or set any bit in the microphone preamplifier gain registers PALEN[1:0] or PAREN[1:0]). This enables the 2.2k pullup. Once the jack has been inserted and the type of accessory determined, set JDWK = 1 to save power. Once the plug is removed, set JDWK = 0.
Table 21. Jack Sense (JKSNS)
JKSNS[1:0] 00 01 10 11 JACKSNS is below VTH2 (low). JACKSNS is between VTH1 and VTH2 (mid). Invalid. JACKSNS is above VTH1 (high). DESCRIPTION
______________________________________________________________________________________
51
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
LOUTP GND MIC HPR HPL ROUTP MICBIAS JACKSNS/AUX
MICLP LOUTN
Figure 8. Typical Configuration for Headset Detection
Table 22. Debounce Time
JDEB 00 01 10 11 DEBOUNCE (ms) 25 50 100 200
(> 95% x MICBIAS), mid, or low (< 10% x MICBIAS). When connected to the microphone pin of the headset jack, this window comparator allows detection of: * No headset (high) * Cellular headset with microphone (high mid) * Stereo headset without microphone (high low) * Cellular headset button press (mid low mid) * Headset removal (low or mid high) Jack removal: A jack is present. All output poles (headphones/line outs) are assumed driven by a low impedance amplifier. All input poles (microphones) are assumed to be biased with a voltage above ground but below 95% of the MICBIAS voltage. For the MAX9880A to sense when a jack is removed, the JACKSNS pin must be connected to the jack in such a way as to ensure either the JACKSNS pin gets pulled above 95% of MICBIAS (as would happen if JACKSNS is hooked to a microphone pole) or it changes state from low to high or vice versa (as would happen if JACKSNS is hooked to a ground pole which goes high impedance when the jack is removed, or is hooked to a regular jack insertion tab that shorts to ground when the jack is removed). Subsequently, IRQ is pulled low. Jack absent: After an interrupt has been sent to the system controller, the I2C must indicate unambiguously that a jack is not present when the I2C registers are read. This is indicated by reading the status of the JKSNS[1:0] I2C read bits.
Debounce (JDEB) Configures the JDET debounce time for changes to JKSNS[1:0] according to Table 22. For jack plug insertion/removal, the sequence of events is as follows: Jack insertion: No jack is present. The MAX9880A has a power supply and is in low-power sleep mode (LOUTP/ROUTP are high impedance). When the JDETEN I 2 C bit is set, the JACKSNS pin has weak pullups to MICVDD. When a jack is subsequently inserted, JACKSNS should change state (indicated by I2C bits JKSNS[1:0]), and this causes the IRQ pin to be pulled low, which can trigger a system wakeup.
Jack present: After an interrupt has been sent to the system controller, the I2C must indicate unambiguously that a jack is present when the I2C registers are read. This is done with the JDET I2C bit, which goes high when there is a change of state of the JKSNS[1:0] bits. The MAX9880A jack-detect system monitors the JACKSNS pin and reports the voltage level as high
52
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Table 23. Headset Detect Configuration
SHDN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 MICBIAS -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 1 1 1 1 JDWK 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 -- -- -- -- JACK ACTION FROM None None Headset Headphone None None Headset Headphone None None Headset Headphone None None Headset Headphone None None Headset Headphone TO Headset Headphone None None Headset Headphone None None Headset Headphone None None Headset Headphone None None Headset Headphone None None FROM 11 11 01 00 11 11 00 00 11 11 01 00 11 11 00 00 11 11 01 00 JKSNS TO 01 00 11 11 00 00 11 11 01 00 11 11 00 00 11 11 01 00 11 11 IRQ TOGGLES? IJDET = 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes IJDET = 0 No No No No No No No No No No No No No No No No No No No No
Note: JDETEN = 1; MICBIAS enable; any bit of PALEN/PAREN set.
______________________________________________________________________________________
53
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Headphone Modes The MAX9880A's headphone amplifier supports differential, single-ended, and capacitorless output modes, as shown in Figure 9. In each mode, the amplifier can be configured for stereo or mono operation. The singleended mode optionally includes click-and-pop reduction to eliminate the click-and-pop that would normally be caused by the output coupling capacitor. When click-and-pop reduction is not required leave LOUTN and ROUTN unconnected.
DIFFERENTIAL
CAPACITORLESS
SINGLE-ENDED 220F
LOUTP LOUTN
LOUTP LOUTN
LOUTP LOUTN 1F
220F ROUTP ROUTN ROUTP ROUTN ROUTP ROUTN 1F
OPTIONAL COMPONENTS REQUIRED FOR CLICK-AND-POP SUPPRESSION ONLY.
Figure 9. Headphone Amplifier Modes
Table 24. Mode Configuration Register
REGISTER Mode Jack Detect B7 DSLEW JDETEN B6 VSEN 0 B5 ZDEN JDWK B4 0 0 B3 0 0 0 B2 B1 HPMODE JDEB B0 REGISTER ADDRESS (SEE NOTE) 0x24 0x25
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS DSLEW FUNCTION Digital Volume Slew Speed 0 = Digital volume changes are slewed over 10ms. 1 = Digital volume changes are slewed over 80ms. Volume Change Smoothing 0 = Volume changes slew through all intermediate values. 1 = Volume changes occur in one step. Line Input Zero-Crossing Detection 0 = Line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero crossing occurs. 1 = Line input volume changes occur immediately.
VSEN
ZDEN
54
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 24. Mode Configuration Register (continued)
BITS Headphone Amplifier Mode HPMODE 000 001 010 HPMODE 011 100 101 110 111 Note: In mono operation, the right amplifier is disabled. Jack-Detection Enable SHDN = 0: Sleep Mode. Enables pullups on JACKSNS/AUX to detect jack insertion. SHDN = 1: Normal Mode. Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes. Note: AUXEN must be set to 0 for jack detection to function. Jack-Sense Weak Pullup. Enables an internal pullup. Set JDWK = 1 to enable an internal 5A current source. Set JDWK = 0 for external pullup. Jack Detect Debounce. Configures the JDET debounce time for changes to JKSNS[1:0] according to information below. JDEB JDEB 00 01 10 11 DEBOUNCE TIME (ms) 25 50 100 200 Stereo differential Mono (left) differential Stereo capacitorless Mono (left) capacitorless Stereo single-ended (clickless) Mono (left) single-ended (clickless) Stereo single-ended (fast turn-on) Mono (left) single-ended (fast turn-on) MODE FUNCTION
MAX9880A
JDETEN
JDWK
Power Management
The MAX9880A includes complete power management control to minimize power usage. The DAC and both ADCs can be independently enabled so that only the required circuitry is active.
Revision Code
The MAX9880A includes a revision code to allow easy identification of the device revision. Revision code at register address 0xFF is not accessible through the SPI interface and so the revision code is accessible through SPI at an additional address of 0x14 (0x14-SPI address). The current revision code is 0x42.
______________________________________________________________________________________
55
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Table 25. Power Management Register
REGISTER Enable System Shutdown B7 LNLEN SHDN B6 LNREN 0 B5 LOLEN 0 B4 LOREN 0 B3 DALEN XTEN B2 DAREN XTOSC B1 ADLEN 0 B0 ADREN 0 REGISTER ADDRESS (SEE NOTE) 0x26 0x27
Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
BITS FUNCTION Left-Line Input Enable. Enables the left-line input preamp and automatically enables the left and right headphone amplifiers. If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and right headphone amplifier. Note: Control of the right headphone amplifier can be overridden by HPMODE. Right-Line Input Enable. Enables the right-line input preamp and automatically enables the right headphone amplifiers. Note: Control of the right headphone amplifier can be overridden by HPMODE. Left-Line Output Enable. Enables the left-line output. Right-Line Output Enable. Enables the right-line output. Left DAC Enable. Enables the left DAC and automatically enables the left and right headphone amplifiers. If DAREN = 0, the left DAC signal is also routed to the right headphone amplifier. Note: Control of the right headphone amplifier can be overridden by HPMODE. Right DAC Enable. Right DAC operation requires DALEN = 1. Left ADC Enable. Right ADC Enable. Enabling the right ADC must be done in the same I2C write operation that enables the left ADC. The right ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must be toggled to disable the right ADC in this case. Right ADC operation requires ADLEN = 1. Shutdown. Places the device in low power shutdown mode. Crystal Clock Enable 1 = Output of crystal oscillator and buffer routed to the clock prescaler. MCLK input disabled. 0 = MCLK input routed to the clock prescaler. Crystal oscillator and buffer disabled. Crystal Clock Source 1 = Disables the internal crystal oscillator. Provide an external clock on X1. 0 = Enables the internal crystal oscillator. Attach a crystal between X1 and X2. XTOSC is ignored if XTEN = 0.
LNLEN
LNREN LOLEN LOREN DALEN DAREN ADLEN ADREN SHDN XTEN
XTOSC
Table 26. Revision Code Register
REGISTER Revision ID Revision ID B7 B6 B5 B4 REV REV B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE) 0x14 0xFF
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
56
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
tCSS CS tCP tCSW tCL SCLK tCH tDEN tDO tCSH
DIN tDS tDH tDZ
DOUT
Figure 10. SPI Interface Timing Diagram
CS
SCLK
DIN
R/W HIGH-Z
ADDR9
ADDR0
UNUSED4
UNUSED0
D7 1 DATA BYTE
D0
DOUT
Figure 11. Writing 1 Byte of Data to the MAX9880A
Serial Peripheral Interface (SPI)
Chip Select (CS) The MAX9880A SPI interface is active only when CS is low. When CS is high, the MAX9880A three-states the DOUT output and resets the internal SPI logic. If CS goes high in the middle of an SPI transfer, all the data is discarded. When CS is low, unless the register address is correctly decoded by the MAX9880A, the DOUT output is three-stated. Serial Clock (SCLK) The SPI master provides the SCLK signal to clock the SPI interface. SCLK has an upper frequency limit of 25MHz. The MAX9880A samples the DIN input data on the falling edge of SCLK and changes the output data on the rising edge of SCLK. The MAX9880A ignores SCLK transitions when CS is high.
Serial-Data In (DIN) and Serial-Data Out (DOUT) The SPI frame is organized into 24 bits. The first 16 bits consist of the R/W enable bit, followed by the 10 register address bits and 5 unused bits. The next 8 bits are data bits, sent most significant bit first. For an SPI write transfer, write a 1 to the R/W bit, followed by the 10 register address bits, 5 unused bits, then the 8 data bits. Figure 11 illustrates the proper frame format for writing one byte of data to the MAX9880A. Additional 24-bit frames can be sent while CS remains low. The DOUT output is three-stated during a write operation. For an SPI read transfer, write a zero to the R/W bit, followed by the 10 register address bits and 5 unused bits. Any data sent after the register address bits are ignored. The internal contents of the register being read
______________________________________________________________________________________
57
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
CS
SCLK
DIN
R/W HIGH-Z
ADDR9
ADDR0
UNUSED4
UNUSED0
DOUT
D7 1 DATA BYTE
D0
Figure 12. Reading 1 Byte of Data from the MAX9880A
CS
SCLK
DIN
R/W HIGH-Z
ADDR9
ADDR0
UNUSED4
UNUSED0
DOUT
D7 1 DATA BYTE
D0
D7 1 DATA BYTE
D0
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 13. Reading n Bytes of Data from the MAX9880A
do not change until the transfer is complete. The DOUT output is three-stated when writing the register address bits. If the correct register address is decoded, DOUT is driven low at the first rising clock edge after the first unused bit. Figure 12 illustrates the proper frame format for reading 1 byte of data from the MAX9880A. When reading data from the MAX9880A, the address pointer autoincrements by one register address if CS is held low after reading the first 8 data bits. For each subsequent eight clock cycles, a byte of data is read. This autoincrement feature allows a master to read sequential registers within one continuous SPI register address range from 0x200 to 0x227. The register address does not autoincrement if a read is initiated at a register address lower than 0x200. If the register address increments beyond 0x227, the DOUT output is three-stated. Figure 13 illustrates the proper format for reading multiple bytes of data.
I2C Serial Interface
The MAX9880A features an I2C/SMBusTM-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9880A and the master at clock rates up to 400kHz. Figure 14 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX9880A by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or repeated START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9880A is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9880A transmits the proper slave address followed by a series of nine SCL pulses. The MAX9880A transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read
SMBus is a trademark of Intel Corp.
58
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
SDA tSU,STA tHD,DAT tHIGH tBUF tHD,STA tSP tSU,STO
tLOW
tSU,DAT
SCL tHD,STA tR START CONDITION
tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 14. 2-Wire Interface Timing Diagram
S
Sr
P
SCL
SDA
Figure 15. START, STOP, and Repeated START Conditions
sequence is framed by a START (S) or repeated START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an opendrain output. A pullup resistor, typically greater than 500, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9880A from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals.
START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 15). A START condition from the master signals the beginning of a transmission to the MAX9880A. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a repeated START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9880A recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition.
Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section).
______________________________________________________________________________________
59
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
START CONDITION SCL 1 28 NOT ACKNOWLEDGE SDA ACKNOWLEDGE CLOCK PULSE FOR ACKNOWLEDGMENT
9
Figure 16. Acknowledge
ACKNOWLEDGE FROM MAX9880A B7 ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9880A REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 17. Writing 1 Byte of Data
Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the MAX9880A, the seven most significant bits are 0011000. Setting the read/write bit to 1 (slave address = 0x31) configures the MAX9880A for read mode. Setting the read/write bit to 0 (slave address = 0x30) configures the MAX9880A for write mode. The address is the first byte of information sent to the MAX9880A after the START (S) condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9880A uses to handshake receipt each byte of data when in write mode (see Figure 16). The MAX9880A pulls down SDA during the entire mastergenerated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication.
60
The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX9880A is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9880A, followed by a STOP (P) condition.
Write Data Format A write to the MAX9880A includes transmission of a START condition, the slave address with the R/W bit set to 0, 1 byte of data to configure the internal register address pointer, 1 or more bytes of data, and a STOP condition. Figure 17 illustrates the proper frame format for writing 1 byte of data to the MAX9880A. Figure 18 illustrates the frame format for writing n bytes of data to the MAX9880A. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9880A. The MAX9880A acknowledges receipt of the address byte during the master-generated 9th SCL pulse.
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
The second byte transmitted from the master configures the MAX9880A's internal register address pointer. The pointer tells the MAX9880A where to write the next byte of data. An acknowledge pulse is sent by the MAX9880A upon receipt of the address pointer data. The third byte sent to the MAX9880A contains the data that is written to the chosen register. An acknowledge pulse from the MAX9880A signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP (P) condition. Register addresses greater than 0x17 are reserved. Do not write to these addresses. the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9880A's slave address with the R/W bit set to 0 followed by the register address. A repeated START (Sr) condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9880A then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 19 illustrates the frame format for reading 1 byte from the MAX9880A. Figure 20 illustrates the frame format for reading multiple bytes from the MAX9880A.
MAX9880A
Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9880A acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START (S) command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX9880A is the contents of register 0x00. Transmitted data is valid on
ACKNOWLEDGE FROM MAX9880A ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS R/W 0 B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9880A A REGISTER ADDRESS A DATA BYTE 1 1 BYTE A
ACKNOWLEDGE FROM MAX9880A B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE n 1 BYTE
A
P
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 18. Writing n Bytes of Data
NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS R/W 0 ACKNOWLEDGE FROM MAX9880A REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9880A Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 19. Reading 1 Byte of Data
______________________________________________________________________________________
61
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS R/W 0 ACKNOWLEDGE FROM MAX9880A REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9880A Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A
REPEATED START
Figure 20. Reading n Bytes of Data
Applications Information
Proper layout and grounding are essential for optimum performance. When designing a PCB for the MAX9880A, partition the circuitry so that the analog sections of the MAX9880A are separated from the digital sections. This ensures that the analog audio traces are not routed near digital traces. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect AGND and DGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. Ground the bypass capacitors on MICBIAS, REG, PREG, and REF directly to the ground plane with minimum trace length. Also be sure to minimize the path length to AGND. Bypass AVDD directly to AGND.
Connect all digital I/O termination to the ground plane with minimum path length to DGND. Bypass DVDD and DVDDS1 directly to DGND. Route microphone signals from the microphone to the MAX9880A as a differential pair, ensuring that the positive and negative signals follow the same path as closely as possible with equal trace length. When using single-ended microphones or other single-ended audio sources, ground the negative microphone input as close to the audio source as possible and then treat the positive and negative traces as differential pairs. The MAX9880A TQFN package features an exposed thermal pad on its underside. Connect the exposed thermal pad to AGND. An evaluation kit (EV kit) is available to provide an example layout for the MAX9880A. The EV kit allows quick setup of the MAX9880A and includes easy-to-use software allowing all internal registers to be controlled.
Startup Sequences
Table 27. Clock Initialization (Perform Before Any Playback or Record Setup)
SEQUENCE 1 2 3 SHDN = 0 Configure clocks Configure digital audio interface DESCRIPTION REGISTERS 0x27 0x05, 0x06, 0x07, 0x0B, 0x0C 0x08, 0x09, 0x0A, 0x0D, 0x0E, 0x0F
Table 28. Music Playback
SEQUENCE 1 2 3 4 5 6 7 8 9 DESCRIPTION Select DAC audio source Select music filters Set output volume Set line output volume Select headphone mode Enable line outputs and DAC as required Enable LRCLK and BCLK (if operating in slave mode) Enable MAX9880A Enable external amplifier (if using) REGISTERS 0x10 0x11 0x1C, 0x1D 0x1E, 0x1F 0x24 0x26 N/A 0x27 N/A
62
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Table 29. Line Input Playback
SEQUENCE 1 2 3 4 5 6 7 Set line input gain Set volume Set line output volume (if using) Select headphone mode Enable line outputs and line inputs as required Enable MAX9880A Enable external amplifier (if using) DESCRIPTION REGISTERS 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x24 0x26 0x27 N/A
MAX9880A
Table 30. Line Input Playback with Record
SEQUENCE 1 2 3 4 5 6 7 8 9 10 Select music filters Set line input gain Set volume Set line output volume (if using) Configure ADC input mixer Select headphone mode Enable line outputs, line inputs, and ADC as required Enable LRCLK and BCLK (if operating in slave mode) Enable MAX9880A Enable external amplifier (if using) DESCRIPTION REGISTERS 0x11 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x22 0x24 0x26 N/A 0x27 N/A
Table 31. Voice Playback
SEQUENCE 1 2 3 4 5 6 7 8 9 Select DAC audio source Select voice filters Set volume Set line output volume (if using) Select headphone mode Enable line outputs and DAC as required Enable LRCLK and BCLK (if operating in slave mode) Enable MAX9880A Enable external amplifier (if using) DESCRIPTION REGISTERS 0x10 0x11 0x1C, 0x1D 0x1E, 0x1F 0x24 0x26 N/A 0x27 N/A
______________________________________________________________________________________
63
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Table 32. Voice Microphone Record
SEQUENCE 1 2 3 4 5 6 7 8 9 Select voice filters Set ADC level to 0dB Configure microphone gain Set line output volume (if using) Configure ADC input mixer Configure MICBIAS voltage Enable ADC Enable LRCLK and BCLK (if operating in slave mode) Enable MAX9880A DESCRIPTION REGISTERS 0x11 0x18, 0x19 0x20, 0x21 0x1E, 0x1F 0x22 0x23 0x26 N/A 0x27
Table 33. Voice Playback with Record
SEQUENCE 1 2 3 4 5 6 7 8 9 Select voice filters Set ADC level to 0dB Configure microphone gain Set line output volume (if using) Configure ADC input mixer Configure MICBIAS voltage Enable ADCs and DACs as required Enable LRCLK and BCLK (if operating in slave mode) Enable MAX9880A DESCRIPTION REGISTERS 0x11 0x18, 0x19 0x20, 0x21 0x1E, 0x1F 0x22 0x23 0x26 N/A 0x27
64
______________________________________________________________________________________
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Example of Register Settings for Music Playback and Voice Duplex Senarios
Music Playback fMCLK = 12.288MHz (master clock supplied to codec), fLRCLK = 48kHz, standard I2S format, codec in slave
mode, music source connected through S2 pins to DAI2 audio path, and output on headphone amplifiers (output capacitorless mode).
MAX9880A
Table 34. Music Playback
SEQUENCE 1 2 3 4 5 6 7 8 9 10 11 12 13 SHDN = 0 Configure system clock Configure DAI2 clock Configure DAI2 clock Configure DAI2 audio path Configure DAI2 audio path Select DAC audio source Select music filters Set output volume (0dB) Set line output volume (muted) Select headphone mode (output capacitorless mode) Enable line outputs and DAC as required Enable MAX9880A DESCRIPTION REGISTER ADDRESS 0x27 0x05 0x0B 0x0C 0x0D 0x0E 0x10 0x11 0x1C, 0x1D 0x1E, 0x1F 0x24 0x26 0x27 REGISTER VALUE 04h 10h 60h 00h 11h 50h 21h 80h 09h 40h 02h 0Ch 84h
Voice Duplex f MCLK = 13MHz (master clock supplied to codec), f LRCLK = 8kHz, TDM/PCM format, codec in slave
mode, voice signals on S1 pins to DAI1 audio path and output on headphone amplifier left (differential mode).
Table 35. Voice Duplex
SEQUENCE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 SHDN = 0 Configure system clock Configure DAI1 clock Configure DAI1 clock Configure DAI1 audio path Configure DAI2 audio path Select DAC audio source Select voice GSM filters Set ADC level to 0dB Configure microphone gain (20dB preamp gain) Set headphone volume Set line output volume (if using) Configure ADC input mixer Configure MICBIAS voltage (2.2V) Select headphone mode Enable line outputs, ADC and DAC as required Enable MAX9880A DESCRIPTION REGISTER ADDRESS 0x27 0x05 0x0B 0x0C 0x0D 0x0E 0x10 0x11 0x18, 0x19 0x20, 0x21 0x1C, 0x1D 0x1E, 0x1F 0x22 0x23 0x24 0x26 0x27 REGISTER VALUE 04h 10h 0Fh 1Fh 04h 30h 21h 33h 03h 54h 09h 40h 50h 01h 01h 0Bh 84h
______________________________________________________________________________________
65
MAX9880A
IRQ
MODE
SCL/SCLK
CS
SDA/DIN
DOUT
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
BCLKS2
LRCLKS2
SDINS2
SDOUTS2
DVDDS1
MICVDD
DVDD
AVDD
PREG
36 (F2) 3 (A2) X1 XTEN, XTOSC 4 (A3) XTAL OSC X2 I2C/SPI SPDMCLK PSCLK FREQ1 CLOCK GEN AUDIO SOURCE SELECTION LINEAR REG SEL1, SEL2
16 (B7)
8 (A4)
7 (A5)
2 (B3)
5 (B4)
1 (B2)
6 (B5)
41 (D1)
40 (E2)
39 (E1)
38 (D3)
37 (F1)
45 (C3)
44 (C2)
43 (C1)
42 (D2)
46 (B1)
9 (A6)
12 (A7) 34 (E3, F3)
2.2F
REF
10 (B6)
REF
DIGITAL AUDIO PATH 1 (8kHz TO 48kHz) PLL1, NI1, REGS 08-OA PLL2, NI2, REGS 0D-0F _DACA: VOLL: 0dB TO -15dB +6dB TO -84dB DCB AUDIO FILTER _DACA: VOLR: 0dB TO -15dB +6dB TO -84dB DCB AUDIO FILTER DSTS MIX/MUX DVST: -9dB TO -69dB MIX SPDMR MIXSPDMR MIX SPDML 1b I/F SPDMDATA MIXSPDML
DIGITAL AUDIO PATH 2 (8kHz TO 96kHz)
1F PREG
REG
13 (C6)
VCM
MAX9880A
MICLP/ DIGMICDATA MXINL ADLEN MIX/MUX ADCL AVFLT MICDG: 0/6/12/18dB VDACG: _DACA: 0/6/12/18dB 0dB TO -15dB VOLR: +6dB TO -84dB VOICE/AUDIO FILTER AVR: +4dB TO -11dB MODE, DVFLT MODE, DVFLT VOICE/AUDIO FILTER VOICE/AUDIO FILTER MODE MIX AVL: +4dB TO -11dB VDACG: _DACA: 0/6/12/18dB 0dB TO -15dB VOLL: +6dB TO -84dB
19 (D7)
PALEN: 0/20/30dB
PGAML: +20dB TO 0dB
MIX/MUX
1F
MICBIAS
17 (B8)
MICBIAS
MIXDAL MIX DAC DALEN MIXDAR MIX DAC DAREN
PVDD
Low-Power, High-Performance Dual I2S Stereo Audio Codec
MIX
FM RECEIVER
66
1.8V 1.8V 1F 1F 1F 1F 1.8V 1.8V 1F 32 HPMODE (E4) LOUTP 31 (F4) 29 HPMODE (E5) LOUTN ROUTP 30 (F5) LOGL: 0dB TO -30dB LOLEN ROUTN MIXINR MODE ADCR ADREN MICDG: 0/6/12/18dB AVFLT VOICE/AUDIO FILTER 26 (E7) LOUTL LOGR: 0dB TO -30dB LOREN 25 (F7) LOUTR 22 (D5) 15 (A8) DGND AGND 27 (E6, F6) PGND HEADPHONE SENSE AUXEN 47 (A1)
1.8V
1F
MICLN/ DIGMICCLK
18 (C7)
SPDMDATA
MICRP/ SPDMDATA
20 (C8)
PAREN: 0/20/30dB
PGAMR: +20dB TO 0dB
MICRN/ SPDMCLK
21 (D8)
SPDMCLK
LINL
23 (E8)
LIGL: +30dB TO 0dB
LNLEN
LINR
24 (F8)
LIGR: +30dB TO 0dB
LNREN JACKSNS/ AUX
______________________________________________________________________________________
Functional Diagram/Typical Operating Circuit
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 WLP 48 TQFN-EP PACKAGE CODE W482A3+1 T4866+1 DOCUMENT NO. 21-0230 21-0141
MAX9880A
______________________________________________________________________________________
67
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
68
______________________________________________________________________________________
QFN THIN.EPS
Low-Power, High-Performance Dual I2S Stereo Audio Codec
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
MAX9880A
______________________________________________________________________________________
69
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A
Revision History
REVISION NUMBER 0 REVISION DATE 7/10 Initial release DESCRIPTION PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
70 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX9880AEWM

	To Download MAX9880AEWM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .